VHDL语言 八段七段数码管轮流显示0-9,不用3-8译码器
时间: 2023-05-14 18:04:49 浏览: 824
可以使用一个计数器和一个数码管驱动器来实现八段七段数码管轮流显示0-9,不需要3-8译码器。具体实现可以使用VHDL语言编写一个计数器模块和一个数码管驱动器模块,然后将它们连接起来。在计数器模块中,可以使用一个计数器来计数0-9,然后将计数器的输出作为数码管驱动器的输入,控制数码管显示相应的数字。
相关问题
VHDL八位七段数码管轮流显示0到9
非常感谢您的提问!以下是VHDL八位七段数码管轮流显示0到9的代码:
```
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity eight_digit_display is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
data : in STD_LOGIC_VECTOR (3 downto 0);
seg : out STD_LOGIC_VECTOR (6 downto 0);
an : out STD_LOGIC_VECTOR (7 downto 0));
end eight_digit_display;
architecture Behavioral of eight_digit_display is
signal count : integer range 0 to 7 := 0;
signal display : STD_LOGIC_VECTOR (3 downto 0) := "0000";
signal an_count : integer range 0 to 7 := 0;
begin
process (clk, reset)
begin
if reset = '1' then
count <= 0;
display <= "0000";
an_count <= 0;
elsif rising_edge(clk) then
if count = 7 then
count <= 0;
else
count <= count + 1;
end if;
case count is
when 0 => display <= "0000";
when 1 => display <= "0001";
when 2 => display <= "0010";
when 3 => display <= "0011";
when 4 => display <= "0100";
when 5 => display <= "0101";
when 6 => display <= "0110";
when 7 => display <= "0111";
end case;
if an_count = 7 then
an_count <= 0;
else
an_count <= an_count + 1;
end if;
end if;
end process;
process (display, an_count)
begin
case an_count is
when 0 => an <= "11111110";
when 1 => an <= "11111101";
when 2 => an <= "11111011";
when 3 => an <= "11110111";
when 4 => an <= "11101111";
when 5 => an <= "11011111";
when 6 => an <= "10111111";
when 7 => an <= "01111111";
end case;
case display is
when "0000" => seg <= "0000001"; -- 0
when "0001" => seg <= "1001111"; -- 1
when "0010" => seg <= "0010010"; -- 2
when "0011" => seg <= "0000110"; -- 3
when "0100" => seg <= "1001100"; -- 4
when "0101" => seg <= "0100100"; -- 5
when "0110" => seg <= "0100000"; -- 6
when "0111" => seg <= "0001111"; -- 7
when "1000" => seg <= "0000000"; -- 8
when "1001" => seg <= "0000100"; -- 9
when others => seg <= "1111111"; -- off
end case;
end process;
end Behavioral;
```
希望这个代码对您有所帮助!
VHDL18个拨码开关3-8译码器控制数码管的数字显示
以下是VHDL代码:
```
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity decoder is
port (
switches : in std_logic_vector(17 downto 0); -- 18个拨码开关
segments : out std_logic_vector(6 downto 0); -- 数码管7段显示输出
cathodes : out std_logic_vector(3 downto 0) -- 数码管位选控制输出
);
end entity decoder;
architecture behavioral of decoder is
signal binary : std_logic_vector(2 downto 0); -- 3位二进制数,用于控制译码器
begin
-- 3-8译码器的真值表
process(switches)
begin
case switches(17 downto 16) is
when "00" => binary <= "000"; -- switch 17-16 = 00,译码器输出 Y0
when "01" => binary <= "001"; -- switch 17-16 = 01,译码器输出 Y1
when "10" => binary <= "010"; -- switch 17-16 = 10,译码器输出 Y2
when "11" => binary <= "011"; -- switch 17-16 = 11,译码器输出 Y3
end case;
end process;
-- 数码管7段显示的真值表
process(binary, switches)
begin
case binary is
when "000" => -- 译码器输出 Y0
segments <= "00111111"; -- 数字 0
cathodes <= "1110"; -- 第1位数码管
when "001" => -- 译码器输出 Y1
segments <= "00000110"; -- 数字 1
cathodes <= "1101"; -- 第2位数码管
when "010" => -- 译码器输出 Y2
segments <= "01011011"; -- 数字 2
cathodes <= "1011"; -- 第3位数码管
when "011" => -- 译码器输出 Y3
segments <= "01001111"; -- 数字 3
cathodes <= "0111"; -- 第4位数码管
end case;
end process;
end architecture behavioral;
```
以上代码实现了18个拨码开关控制3-8译码器,进而控制数码管的数字显示。其中,3-8译码器的输出 Y0-Y3 分别对应数字 0-3 的7段显示编码。同时,使用了一个二进制信号 binary 来控制译码器的输出。数码管的位选控制则使用了另外一个信号 cathodes,通过对其赋不同的值来控制不同的数码管显示。