FIG. 3 is a timing diagram illustrating the operation of the pulse width measurement 16 of the present invention. At top the output pulse from AND gate 24 appears and this is a 125 KHz pulse train with pulse width equal to the delay through the delay chain. The 32/33 Mhz clock 12 appears at center. As shown at bottom, the top output pulse from AND gate 24 is sampled by the 32/33 Mhz clock 12 for a fixed period of, for example, one second. This is done by the pulse width measurement block 16. The pulse width measurement block 16 then counts the sampled pulse train to determine the pulse width, and this is output to a hexadecimal display 28 (driven by a display driver 26). The visual readout from the display 28 is thereby updated continuously to display the propagation delay through the delay chain.翻译

图3是一个时序图，说明了本发明的脉冲宽度测量器16的操作。图中顶部出现了AND门24的输出脉冲，它是一个125kHz的脉冲列，脉冲宽度等于延迟链中的延迟。中间显示了32/33MHz时钟12。如底部所示，通过固定时间（例如1秒钟）内，32/33MHz时钟12对AND门24的顶部输出脉冲进行采样。脉冲宽度测量器16随后对采样到的脉冲列进行计数，以确定脉冲宽度，并将其输出到一个十六进制显示器28（由显示驱动器26驱动）。因此，显示器28的视觉读数被连续更新，以显示延迟链的传播延迟。