三相SPWM的Verilog代码

module spwm_generator(
input clk,
input rst,
output reg [7:0] pwm_out
);

reg [7:0] counter = 0;
reg [7:0] tau1 = 128;
reg [7:0] tau2 = 32;
reg [2:0] sector = 0;
reg [1:0] state = 0;

always @(posedge clk or posedge rst) begin
if(rst) begin
counter <= 0;
tau1 <= 128;
tau2 <= 32;
sector <= 0;
state <= 0;
end
else begin
case(state)
0: begin
counter <= counter + 1;
if(counter >= tau1) begin
counter <= 0;
state <= 1;
end
end
1: begin
pwm_out <= 8'd255;
counter <= counter + 1;
if(counter >= tau2) begin
counter <= 0;
state <= 2;
end
end
2: begin
pwm_out <= 8'd0;
counter <= counter + 1;
if(counter >= tau1) begin
counter <= 0;
state <= 3;
end
end
3: begin
if(sector == 0 || sector == 2 || sector == 4) begin
pwm_out <= 8'd255;
end
else begin
pwm_out <= 8'd0;
end
counter <= counter + 1;
if(counter >= tau2) begin
counter <= 0;
sector <= sector + 1;
if(sector >= 6) begin
sector <= 0;
end
state <= 0;
if(sector == 0 || sector == 2 || sector == 4) begin
tau1 <= 128;
tau2 <= 32;
end
else begin
tau1 <= 64;
tau2 <= 16;
end
end
end
endcase
end
end

endmodule