module seg_decode( input wire clk, input wire rst_n, input wire [4:0] seg_value_1, input wire [4:0] seg_value_2, output reg [5:0] sel, output reg [7:0] seg ); parameter CNT_20US = 10'd999; reg [3:0] number; wire [2:0] change_l; wire [2:0] change_h; reg [9:0] cnt; //计时模块 always@(posedge clk or negedge rst_n)begin if(!rst_n)begin cnt <= 10'd0; end else if(cnt == CNT_20US)begin cnt <= 10'd0; end else begin cnt <= cnt + 10'd1; end end always @(posedge clk or negedge rst_n) begin if(!rst_n)begin sel <= 6'b011111; end else if(cnt == CNT_20US)begin sel <= {sel[0],sel[5:1]}; end else begin sel <= sel; end end always @(posedge clk or negedge rst_n) begin if(!rst_n)begin number <= 4'd0; end else begin case(sel) 6'b011111: number <= seg_value_1 % 10; 6'b101111: number <= seg_value_1 / 10; 6'b110111: number <= seg_value_2 % 10; 6'b111011: number <= seg_value_2 / 10; 6'b111101: begin if(seg_value_2 < seg_value_1) number <= 4'd15; else number <= change_l; end 6'b111110: begin if(seg_value_2 < seg_value_1) number <= 4'd14; else number <= change_h; end default:number <= 4'd0; endcase end end always @(posedge clk or negedge rst_n) begin if(!rst_n)begin seg <= 8'b1100_0000; end else begin case(number) 4'd0: seg <= 8'b1100_0000; 4'd1: seg <= 8'b1111_1001; 4'd2: seg <= 8'b1010_0100; 4'd3: seg <= 8'b1011_0000; 4'd4: seg <= 8'b1001_1001; 4'd5: seg <= 8'b1001_0010; 4'd14: seg <= 8'b1000_0110; 4'd15: seg <= 8'b1100_1110; default:seg <= 8'b1100_0000; endcase end end assign change_l = (seg_value_2 - seg_value_1) % 10; assign change_h = (seg_value_2 - seg_value_1) / 10; sel_drive sel_drive_u ( .clk (clk), .rst_n (rst_n), .sel_2 () ); endmodule

这段代码是一个用 Verilog HDL 编写的七段数码管驱动模块。它包括计时模块、数码管位选模块和数码管段选模块。其中，计时模块用于产生定时信号，数码管位选模块用于控制数码管位选信号，数码管段选模块用于根据输入的数值控制数码管的显示。这个模块包括了一些输入输出端口，比如时钟信号 clk、复位信号 rst_n、两个输入数值 seg_value_1 和 seg_value_2，以及两个输出信号 sel 和 seg。

相关问题

写出以下代码的testbench module decode8(clk_50m,rst_n,c,seg,sel,out,led); input[4:0] c; input clk_50m,rst_n; output reg[6:0]out;//共阳，0点亮 output reg[7:0]seg;//共阴，1点亮 output reg[2:0]sel;//位选 output reg[3:0] led; reg[31:0] timer; reg clk_1hz; always@(posedge clk_50m) begin if(~rst_n) begin timer<=0;clk_1hz<=0;end else if(timer==32'd24)//仿真时可调小 begin timer<=0;clk_1hz<=~clk_1hz;end else begin timer<=timer+1;clk_1hz<=clk_1hz;end end always@(c) if(c[4]==0) begin case(c) 5'b00000:begin led=4'b0000; out =7'b1000000; end //0 5'b00001:begin led=4'b0001; out =7'b1111001; end //1 5'b00010:begin led=4'b0010; out =7'b0100100; end //2 5'b00011:begin led=4'b0011; out =7'b0110000; end //3 5'b00100:begin led=4'b0100; out =7'b0011001; end //4 5'b00101:begin led=4'b0101; out =7'b0010010; end //5 5'b00110:begin led=4'b0110; out =7'b0000010; end //6 5'b00111:begin led=4'b0111; out =7'b1111000; end //7 5'b01000:begin led=4'b1000; out =7'b0000000; end //8 5'b01001:begin led=4'b1001; out =7'b0010000; end //9 5'b01010:begin led=4'b1010; out =7'b0001000; end //A 5'b01011:begin led=4'b1011; out =7'b0000011; end //B 5'b01100:begin led=4'b1100; out =7'b1000110; end //C 5'b01101:begin led=4'b1101; out =7'b0010001; end //D 5'b01110:begin led=4'b1110; out =7'b0000110; end //E 5'b01111:begin led=4'b1111; out =7'b0001110; end //F default:begin led=4'b0000; out =7'b1111111; end endcase end else begin led =4'b0000; out =7'b1111111;end always@(posedge clk_1hz) if(c[4]==1) begin case(sel) 3'b000:begin sel =3'b001; seg =8'b01110110; end //H 3'b001:begin sel =3'b010; seg =8'b01111001; end //E 3'b010:begin sel =3'b011; seg =8'b00111000; end //L 3'b011:begin sel =3'b100; seg =8'b00111000; end //L 3'b100:begin sel =3'b101; seg =8'b00111111; end //0 default: begin sel =3'b000; seg=8'b00000000; end endcase end else seg=8'b00000000; endmodule

以下是该代码的testbench：

`timescale 1ns / 1ps

module decode8_tb;

    // Inputs
    reg clk_50m = 0;
    reg rst_n = 0;
    reg [4:0] c = 5'b00000;

    // Outputs
    wire [6:0] out;
    wire [7:0] seg;
    wire [2:0] sel;
    wire [3:0] led;

    // Instantiate the Unit Under Test (UUT)
    decode8 uut (
        .clk_50m(clk_50m), 
        .rst_n(rst_n), 
        .c(c), 
        .seg(seg), 
        .sel(sel), 
        .out(out), 
        .led(led)
    );

    initial begin
        // Initialize Inputs
        clk_50m = 0;
        rst_n = 0;
        c = 5'b00000;

        #100; // Wait 100 ns for reset to finish

        // Reset
        rst_n = 1;

        // Testcase 1: Output should be 0
        c = 5'b00000;
        #100;
        if(out !== 7'b1000000 || led !== 4'b0000) $display("Error in Testcase 1");

        // Testcase 2: Output should be 1
        c = 5'b00001;
        #100;
        if(out !== 7'b1111001 || led !== 4'b0001) $display("Error in Testcase 2");

        // Testcase 3: Output should be 2
        c = 5'b00010;
        #100;
        if(out !== 7'b0100100 || led !== 4'b0010) $display("Error in Testcase 3");

        // Testcase 4: Output should be 3
        c = 5'b00011;
        #100;
        if(out !== 7'b0110000 || led !== 4'b0011) $display("Error in Testcase 4");

        // Testcase 5: Output should be 4
        c = 5'b00100;
        #100;
        if(out !== 7'b0011001 || led !== 4'b0100) $display("Error in Testcase 5");

        // Testcase 6: Output should be 5
        c = 5'b00101;
        #100;
        if(out !== 7'b0010010 || led !== 4'b0101) $display("Error in Testcase 6");

        // Testcase 7: Output should be 6
        c = 5'b00110;
        #100;
        if(out !== 7'b0000010 || led !== 4'b0110) $display("Error in Testcase 7");

        // Testcase 8: Output should be 7
        c = 5'b00111;
        #100;
        if(out !== 7'b1111000 || led !== 4'b0111) $display("Error in Testcase 8");

        // Testcase 9: Output should be 8
        c = 5'b01000;
        #100;
        if(out !== 7'b0000000 || led !== 4'b1000) $display("Error in Testcase 9");

        // Testcase 10: Output should be 9
        c = 5'b01001;
        #100;
        if(out !== 7'b0010000 || led !== 4'b1001) $display("Error in Testcase 10");

        // Testcase 11: Output should be A
        c = 5'b01010;
        #100;
        if(out !== 7'b0001000 || led !== 4'b1010) $display("Error in Testcase 11");

        // Testcase 12: Output should be B
        c = 5'b01011;
        #100;
        if(out !== 7'b0000011 || led !== 4'b1011) $display("Error in Testcase 12");

        // Testcase 13: Output should be C
        c = 5'b01100;
        #100;
        if(out !== 7'b1000110 || led !== 4'b1100) $display("Error in Testcase 13");

        // Testcase 14: Output should be D
        c = 5'b01101;
        #100;
        if(out !== 7'b0010001 || led !== 4'b1101) $display("Error in Testcase 14");

        // Testcase 15: Output should be E
        c = 5'b01110;
        #100;
        if(out !== 7'b0000110 || led !== 4'b1110) $display("Error in Testcase 15");

        // Testcase 16: Output should be F
        c = 5'b01111;
        #100;
        if(out !== 7'b0001110 || led !== 4'b1111) $display("Error in Testcase 16");

        // Testcase 17: Invalid input, output should be 1111111
        c = 5'b11011;
        #100;
        if(out !== 7'b1111111 || led !== 4'b0000) $display("Error in Testcase 17");

        // Testcase 18: Display H on the 1st segment
        c = 5'b10000;
        sel = 3'b000;
        #100;
        if(seg !== 8'b01110110) $display("Error in Testcase 18");

        // Testcase 19: Display E on the 2nd segment
        c = 5'b10000;
        sel = 3'b001;
        #100;
        if(seg !== 8'b01111001) $display("Error in Testcase 19");

        // Testcase 20: Display L on the 3rd segment
        c = 5'b10000;
        sel = 3'b010;
        #100;
        if(seg !== 8'b00111000) $display("Error in Testcase 20");

        // Testcase 21: Display L on the 4th segment
        c = 5'b10000;
        sel = 3'b011;
        #100;
        if(seg !== 8'b00111000) $display("Error in Testcase 21");

        // Testcase 22: Display 0 on the 5th segment
        c = 5'b10000;
        sel = 3'b100;
        #100;
        if(seg !== 8'b00111111) $display("Error in Testcase 22");

        // Testcase 23: Invalid input, no segment should be active
        c = 5'b11011;
        sel = 3'b000;
        #100;
        if(seg !== 8'b00000000) $display("Error in Testcase 23");
    end

    always #10 clk_50m <= ~clk_50m;

endmodule