module seg_decode( input wire clk, input wire rst_n, input wire [4:0] seg_value_1, input wire [4:0] seg_value_2, output reg [5:0] sel, output reg [7:0] seg ); parameter CNT_20US = 10'd999; reg [3:0] number; wire [2:0] change_l; wire [2:0] change_h; reg [9:0] cnt; //计时模块 always@(posedge clk or negedge rst_n)begin if(!rst_n)begin cnt <= 10'd0; end else if(cnt == CNT_20US)begin cnt <= 10'd0; end else begin cnt <= cnt + 10'd1; end end always @(posedge clk or negedge rst_n) begin if(!rst_n)begin sel <= 6'b011111; end else if(cnt == CNT_20US)begin sel <= {sel[0],sel[5:1]}; end else begin sel <= sel; end end always @(posedge clk or negedge rst_n) begin if(!rst_n)begin number <= 4'd0; end else begin case(sel) 6'b011111: number <= seg_value_1 % 10; 6'b101111: number <= seg_value_1 / 10; 6'b110111: number <= seg_value_2 % 10; 6'b111011: number <= seg_value_2 / 10; 6'b111101: begin if(seg_value_2 < seg_value_1) number <= 4'd15; else number <= change_l; end 6'b111110: begin if(seg_value_2 < seg_value_1) number <= 4'd14; else number <= change_h; end default:number <= 4'd0; endcase end end always @(posedge clk or negedge rst_n) begin if(!rst_n)begin seg <= 8'b1100_0000; end else begin case(number) 4'd0: seg <= 8'b1100_0000; 4'd1: seg <= 8'b1111_1001; 4'd2: seg <= 8'b1010_0100; 4'd3: seg <= 8'b1011_0000; 4'd4: seg <= 8'b1001_1001; 4'd5: seg <= 8'b1001_0010; 4'd14: seg <= 8'b1000_0110; 4'd15: seg <= 8'b1100_1110; default:seg <= 8'b1100_0000; endcase end end assign change_l = (seg_value_2 - seg_value_1) % 10; assign change_h = (seg_value_2 - seg_value_1) / 10; sel_drive sel_drive_u ( .clk (clk), .rst_n (rst_n), .sel_2 () ); endmodule
时间: 2024-03-19 20:42:22 浏览: 15
这段代码是一个用 Verilog HDL 编写的七段数码管驱动模块。它包括计时模块、数码管位选模块和数码管段选模块。其中,计时模块用于产生定时信号,数码管位选模块用于控制数码管位选信号,数码管段选模块用于根据输入的数值控制数码管的显示。这个模块包括了一些输入输出端口,比如时钟信号 clk、复位信号 rst_n、两个输入数值 seg_value_1 和 seg_value_2,以及两个输出信号 sel 和 seg。
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module ram_write ( input wire sys_clk , input wire sys_rst_n , input wire cnt_rcd, input wire [7:0] seg_cnt_data0 , input wire [7:0] seg_cnt_data1 , input wire [7:0] seg_cnt_data2 , input wire [7:0] seg_cnt_data3 , input wire [7:0] seg_cnt_data4 , input wire [7:0] seg_cnt_data5 , output reg [4:0] addr, output reg write_en , output reg [7:0] data_in ); reg [3:0] bite ; reg [3:0] times=0; always @(posedge sys_clk or negedge sys_rst_n) begin if (!sys_rst_n) begin write_en <= 1'b0 ; end else if (cnt_rcd) begin write_en <= 1'b1; times <= times + 1; end else begin write_en <= 1'b0; end end always @(posedge sys_clk or negedge sys_rst_n) if(!sys_rst_n) begin bite <='d0; addr <='d0; data_in <='d0; end else if(write_en) begin case(bite) 'd0: begin addr <= 2'd0+6times ; data_in<= seg_cnt_data0 ; bite<=bite + 1 ; end 'd1: begin addr <= 2'd1+6times ; data_in<= seg_cnt_data1; bite<=bite + 1 ; end 'd2: begin addr <= 2'd2+6times ; data_in<= seg_cnt_data2 ; bite<=bite + 1 ; end 'd3: begin addr <= 2'd3+6times ; data_in<= seg_cnt_data3 ; bite<=bite + 1 ; end 'd4: begin addr <= 2'd4+6times ; data_in<= seg_cnt_data4 ; bite<=bite + 1 ; end 'd5: begin addr <= 2'd5+6times ; data_in<= seg_cnt_data5 ; bite<=bite + 1 ; end default: ; endcase end endmodule修改代码
根据您提供的代码,我发现在更新 `addr` 时,使用的是 `6times`,这里应该是 `6*times`,需要在乘法符号前面加上 `*`,以正确计算地址。请尝试修改如下代码:
```
module ram_write (
input wire sys_clk,
input wire sys_rst_n,
input wire cnt_rcd,
input wire [7:0] seg_cnt_data0,
input wire [7:0] seg_cnt_data1,
input wire [7:0] seg_cnt_data2,
input wire [7:0] seg_cnt_data3,
input wire [7:0] seg_cnt_data4,
input wire [7:0] seg_cnt_data5,
output reg [4:0] addr,
output reg write_en,
output reg [7:0] data_in
);
reg [3:0] bite;
reg [3:0] times = 0;
always @(posedge sys_clk or negedge sys_rst_n) begin
if (!sys_rst_n) begin
write_en <= 1'b0;
end else if (cnt_rcd) begin
write_en <= 1'b1;
times <= times + 1;
end else begin
write_en <= 1'b0;
end
end
always @(posedge sys_clk or negedge sys_rst_n) begin
if (!sys_rst_n) begin
bite <= 'd0;
addr <= 'd0;
data_in <= 'd0;
end else if (write_en) begin
case (bite)
'd0: begin
addr <= 2'd0 + 6 * times;
data_in <= seg_cnt_data0;
bite <= bite + 1;
end
'd1: begin
addr <= 2'd1 + 6 * times;
data_in <= seg_cnt_data1;
bite <= bite + 1;
end
'd2: begin
addr <= 2'd2 + 6 * times;
data_in <= seg_cnt_data2;
bite <= bite + 1;
end
'd3: begin
addr <= 2'd3 + 6 * times;
data_in <= seg_cnt_data3;
bite <= bite + 1;
end
'd4: begin
addr <= 2'd4 + 6 * times;
data_in <= seg_cnt_data4;
bite <= bite + 1;
end
'd5: begin
addr <= 2'd5 + 6 * times;
data_in <= seg_cnt_data5;
bite <= bite + 1;
end
default: ;
endcase
end
end
endmodule
```
请尝试使用上述代码,看看问题是否得到解决。
module seven_tube(clk, rst_n, data_in, sel, seg); input clk; input rst_n; input [23:0] data_in; //6个数码管显示:24位数据 output [2:0] sel; //数码管位选信号 output [7:0] seg; //数码管段选信号 wire clk_1khz; freq freq_dut( .clk(clk), .rst_n(rst_n), .clk_out(clk_1khz) ); seg_ctrl_v2 seg_ctrl_v2_dut( .clk_1khz(clk_1khz), .rst_n(rst_n), .data_in(data_in), .sel(sel), .seg(seg) ); endmodule
这段Verilog代码实现了一个七段数码管模块,用于显示数字。模块接收时钟信号`clk`、复位信号`rst_n`、24位的数据信号`data_in`,以及输出位选信号`sel`和段选信号`seg`。
首先,代码中实例化了一个频率分频模块`freq_dut`,将输入时钟信号`clk`和复位信号`rst_n`连接到该模块,并通过输出信号`clk_out`获得1kHz的时钟信号`clk_1khz`。这个1kHz的时钟信号用于驱动七段数码管的刷新。
接下来,代码实例化了一个`seg_ctrl_v2`模块,将1kHz的时钟信号`clk_1khz`、复位信号`rst_n`、24位的数据信号`data_in`以及输出的位选信号`sel`和段选信号`seg`连接到该模块。这个模块将根据输入的数据信号控制七段数码管的显示。
这段代码是一个简单的七段数码管模块的实现,你可以根据具体的需求进行修改和扩展。