给我写一个verilog状态机

module fsm (
input clk,
input reset,
output reg [1:0] state_out,
input [1:0] input_data
);

//定义状态
parameter STATE_A = 2'b00;
parameter STATE_B = 2'b01;
parameter STATE_C = 2'b10;

//定义状态转移条件
parameter CONDITION_1 = 2'b00;
parameter CONDITION_2 = 2'b01;
parameter CONDITION_3 = 2'b10;

//定义状态机状态寄存器
reg [1:0] state_reg;

//初始化状态机状态
initial begin
state_reg = STATE_A;
state_out = state_reg;
end

//状态机状态转移逻辑
always @(posedge clk) begin
if (reset) begin
state_reg <= STATE_A;
end else begin
case (state_reg)
STATE_A: begin
if (input_data == CONDITION_1) begin
state_reg <= STATE_B;
end else begin
state_reg <= STATE_A;
end
end
STATE_B: begin
if (input_data == CONDITION_2) begin
state_reg <= STATE_C;
end else begin
state_reg <= STATE_B;
end
end
STATE_C: begin
if (input_data == CONDITION_3) begin
state_reg <= STATE_A;
end else begin
state_reg <= STATE_C;
end
end
default: begin
state_reg <= STATE_A;
end
endcase
end
end

//状态机状态输出
always @(posedge clk) begin
state_out <= state_reg;
end

endmodule