请给出实现以下逻辑的verilog代码：输入信号通过温度计码产生逻辑产生了8位的温度计码，经过8-3编码器生成3位的二进制码，在经过模8加法器生成三位的二进制指针，该指针通过寄存器寄存，由指针和输入的温度计码通过桶形移位器共同决定8位DWA算法的选择输出，通过输出码来决定选取的DAC单位元件，并给出另一段针对上述代码的可以使用vivado进行测试和仿真的的testbench代码

以下是实现该逻辑的Verilog代码：

module Temperature_Control(
    input [7:0] temperature_code,
    output reg [7:0] dac_output
);

reg [2:0] pointer;
reg [7:0] dwa_output;
reg [2:0] dwa_select;

// 8-3编码器
always @(*) begin
    case (temperature_code)
        8'b00000000: pointer = 3'b000;
        8'b00000001: pointer = 3'b001;
        8'b00000011: pointer = 3'b010;
        8'b00000111: pointer = 3'b011;
        8'b00001111: pointer = 3'b100;
        8'b00011111: pointer = 3'b101;
        8'b00111111: pointer = 3'b110;
        8'b01111111: pointer = 3'b111;
        default: pointer = 3'b000;
    endcase
end

// 模8加法器
always @(posedge clk) begin
    dwa_select <= (pointer + temperature_code) % 8;
end

// 桶形移位器
always @(posedge clk) begin
    case (dwa_select)
        3'b000: dwa_output <= temperature_code;
        3'b001: dwa_output <= {temperature_code[6:0], temperature_code[7]};
        3'b010: dwa_output <= {temperature_code[5:0], temperature_code[7:6]};
        3'b011: dwa_output <= {temperature_code[4:0], temperature_code[7:5]};
        3'b100: dwa_output <= {temperature_code[3:0], temperature_code[7:4]};
        3'b101: dwa_output <= {temperature_code[2:0], temperature_code[7:3]};
        3'b110: dwa_output <= {temperature_code[1:0], temperature_code[7:2]};
        3'b111: dwa_output <= {temperature_code[0], temperature_code[7:1]};
    endcase
end

// DAC选择器
always @(posedge clk) begin
    case (dwa_output)
        8'b00000000: dac_output <= 8'h00;
        8'b00000001: dac_output <= 8'h01;
        8'b00000010: dac_output <= 8'h02;
        //...
        8'b11111110: dac_output <= 8'hFE;
        8'b11111111: dac_output <= 8'hFF;
        default: dac_output <= 8'h00;
    endcase
end

endmodule

以下是针对该Verilog代码的测试和仿真的testbench代码：

module Temperature_Control_tb;

reg [7:0] temperature_code;
wire [7:0] dac_output;

Temperature_Control dut (
    .temperature_code(temperature_code),
    .dac_output(dac_output)
);

initial begin
    $dumpfile("Temperature_Control_tb.vcd");
    $dumpvars(0, Temperature_Control_tb);

    temperature_code = 8'b00000000;
    #10 temperature_code = 8'b00000001;
    #10 temperature_code = 8'b00000011;
    #10 temperature_code = 8'b00000111;
    #10 temperature_code = 8'b00001111;
    #10 temperature_code = 8'b00011111;
    #10 temperature_code = 8'b00111111;
    #10 temperature_code = 8'b01111111;
    #10 $finish;
end

endmodule

该testbench代码会对输入信号temperature_code进行变化，观察输出信号dac_output是否符合预期。可以使用Vivado进行仿真和波形查看，以确保Temperature_Control模块的正确性。