写一段4字节发送的Verilog收发程序

module tx_rx (
input clk,
input reset,
input [3:0] tx_data,
output reg [3:0] rx_data
);

reg [3:0] temp_data;

always @(posedge clk) begin
if(reset) begin
temp_data <= 4'b0;
rx_data <= 4'b0;
end else begin
temp_data <= tx_data;
rx_data <= temp_data;
end
end

endmodule