vhdl语言实现数字钟 具有清零 暂停功能

下面是具有清零和暂停功能的数字钟 VHDL 代码：

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity digital_clock is
    port( clk : in std_logic;
          rst : in std_logic;
          start_stop : in std_logic;
          clear : in std_logic;
          hour : out std_logic_vector(3 downto 0);
          minute : out std_logic_vector(5 downto 0);
          second : out std_logic_vector(5 downto 0)
    );
end digital_clock;

architecture behavioral of digital_clock is

    signal count : unsigned(23 downto 0) := (others => '0');
    signal sec : unsigned(5 downto 0) := (others => '0');
    signal min : unsigned(5 downto 0) := (others => '0');
    signal hr : unsigned(3 downto 0) := (others => '0');
    signal pause : std_logic := '0';

begin
    process(clk, rst)
    begin
        if rst = '1' then
            count <= (others => '0');
            sec <= (others => '0');
            min <= (others => '0');
            hr <= (others => '0');
            pause <= '0';
        elsif rising_edge(clk) then
            if clear = '1' then
                count <= (others => '0');
                sec <= (others => '0');
                min <= (others => '0');
                hr <= (others => '0');
                pause <= '0';
            elsif pause = '0' then
                count <= count + 1;
                if count = 24000000 then
                    sec <= sec + 1;
                    if sec = 60 then
                        sec <= (others => '0');
                        min <= min + 1;
                        if min = 60 then
                            min <= (others => '0');
                            hr <= hr + 1;
                            if hr = 24 then
                                hr <= (others => '0');
                            end if;
                        end if;
                    end if;
                end if;
            end if;
        end if;
    end process;

    hour <= std_logic_vector(to_unsigned(to_integer(hr), 4));
    minute <= std_logic_vector(to_unsigned(to_integer(min), 6));
    second <= std_logic_vector(to_unsigned(to_integer(sec), 6));
    
    process(start_stop, clk)
    begin
        if start_stop = '1' and rising_edge(clk) then
            pause <= not pause;
        end if;
    end process;

end behavioral;

在该代码中，我们添加了两个输入信号 `start_stop` 和 `clear`，分别用于暂停和清零数字钟。在时钟上升沿时，如果 `pause` 信号为 0，那么数字钟会正常计数；否则，数字钟会被暂停。当 `clear` 信号为 1 时，所有计数器都会被清零。

同时，我们还添加了一个 `pause` 信号，用于记录数字钟是否处于暂停状态。当 `start_stop` 信号为 1 且时钟上升沿到来时，`pause` 信号将被翻转，从而实现数字钟的暂停和恢复功能。