Verilog将一个FIFO写数据1-20，并依次读出到FIFO2，FIFO3内

好的，下面是一个简单的 Verilog 实现：

module fifo (
    clk,
    reset,
    data_in,
    write_en,
    data_out,
    read_en
);

parameter WIDTH = 8;
parameter DEPTH = 20;

input clk;
input reset;
input [WIDTH-1:0] data_in;
input write_en;
output reg [WIDTH-1:0] data_out;
input read_en;

reg [WIDTH-1:0] mem [DEPTH-1:0];
reg [WIDTH-1:0] head = 0;
reg [WIDTH-1:0] tail = 0;
reg [WIDTH-1:0] count = 0;

always @(posedge clk) begin
    if (reset) begin
        head <= 0;
        tail <= 0;
        count <= 0;
    end else begin
        if (write_en && count < DEPTH) begin
            mem[head] <= data_in;
            head <= head + 1;
            count <= count + 1;
        end
        if (read_en && count > 0) begin
            data_out <= mem[tail];
            tail <= tail + 1;
            count <= count - 1;
        end
    end
end

endmodule

module testbench;

parameter WIDTH = 8;

reg clk = 0;
always #5 clk = ~clk;

reg reset = 1;
reg [WIDTH-1:0] data_in = 0;
reg write_en = 0;
wire [WIDTH-1:0] data_out = 0;
reg read_en = 0;

fifo dut (
    .clk(clk),
    .reset(reset),
    .data_in(data_in),
    .write_en(write_en),
    .data_out(data_out),
    .read_en(read_en)
);

initial begin
    reset = 0;
    #10;
    reset = 1;
    #10;
    for (int i = 0; i < 20; i = i + 1) begin
        data_in = i + 1;
        write_en = 1;
        #10;
    end
    for (int i = 0; i < 20; i = i + 1) begin
        read_en = 1;
        #10;
        read_en = 0;
    end
end

endmodule

上面的代码描述了一个带有读写时序控制的 FIFO 模块，同时也包含一个简单的测试模块用于对 FIFO 进行数据写入和读出的功能测试。在测试模块中，我们先通过 for 循环将数据 1-20 依次写入到 FIFO 中，然后再通过 for 循环依次将 FIFO 中的数据读出并写入到 FIFO2 和 FIFO3 中。