show me code verilog设计序列发生器

以下是一个简单的 Verilog 设计序列发生器的代码示例：

module sequence_generator(
input clk,
input rst,
output reg [7:] seq
);

reg [2:] state;

always @(posedge clk or posedge rst) begin
if (rst) begin
state <= 3'b000;
seq <= 8'b00000000;
end else begin
case (state)
3'b000: begin
seq <= 8'b00000001;
state <= 3'b001;
end
3'b001: begin
seq <= 8'b00000010;
state <= 3'b010;
end
3'b010: begin
seq <= 8'b00000100;
state <= 3'b011;
end
3'b011: begin
seq <= 8'b00001000;
state <= 3'b100;
end
3'b100: begin
seq <= 8'b00010000;
state <= 3'b101;
end
3'b101: begin
seq <= 8'b00100000;
state <= 3'b110;
end
3'b110: begin
seq <= 8'b01000000;
state <= 3'b111;
end
3'b111: begin
seq <= 8'b10000000;
state <= 3'b000;
end
endcase
end
end

endmodule

希望这个代码示例能够帮助你！