do it as vhdl language

Certainly! Below is a summary of the key steps and tasks you need to complete for the EE-Labs-Part2.pdf document, specifically focusing on the VHDL aspects:

### Summary of Key Steps and Tasks

#### 1. **Setting Up the Project**
- Open Vivado and load the project from Part 1.
- Save it as a new project named "Part2" on your U: drive.
- Ensure the correct board is selected by checking the Project Device settings.

#### 2. **Using All Digits on the Display**
- Download `drive_display.vhd` from Canvas.
- Replace the existing display entity with `drive_display`.
- **Entity Declaration**:

     entity drive_display is
         Port (
             CLK100MHZ : in std_logic;
             display : in STD_LOGIC_VECTOR(31 downto 0);
             DIGITS : out STD_LOGIC_VECTOR(7 downto 0);
             SEGMENTS : out STD_LOGIC_VECTOR(7 downto 0)
         );
     end drive_display;

- Test the display by initializing a local variable `display` in your top-level VHDL file and assigning it a recognizable value (e.g., `0x01234567`).

#### 3. **Adding the Display to the ALU Inputs and Outputs**
- Modify the ALU to use the new display for better visibility.
- Assign specific parts of the `display` signal to show different ALU parameters:
- Digit 6: Opcode
- Digit 4: Result
- Digit 2: Second Input
- Digit 0: First Input
- Set the remaining digits to zero.
- Synthesize the design and verify its functionality.

#### 4. **Making Better Use of the Simulator: Testbenches**
- Download `testbench.vhd` from Canvas and add it as a simulation source.
- **Testbench Structure**:

     library IEEE;
     use IEEE.STD_LOGIC_1164.ALL;

     entity tb is
     end tb;

     architecture Behavioral of tb is
         signal CLK100MHZ : std_logic := '0';
         signal BTNL, BTNR, BTNU, BTND, BTNC : std_logic;
         signal SWITCHES : STD_LOGIC_VECTOR(15 downto 0);
         signal LEDS : STD_LOGIC_VECTOR(15 downto 0);
         signal DIGITS : STD_LOGIC_VECTOR(7 downto 0);
         signal SEGMENTS : STD_LOGIC_VECTOR(7 downto 0);

     begin
         uut : entity work.micro(Behavioral)
             port map (
                 CLK100MHZ => CLK100MHZ,
                 BTNL => BTNL,
                 BTNR => BTNR,
                 BTNU => BTNU,
                 BTND => BTND,
                 BTNC => BTNC,
                 SWITCHES => SWITCHES,
                 LEDS => LEDS,
                 DIGITS => DIGITS,
                 SEGMENTS => SEGMENTS
             );

         CLK100MHZ <= not CLK100MHZ after 5 ns;

         process
         begin
             SWITCHES <= "0000000000000000";
             BTNL <= '1';
             wait for 100 ns;
             SWITCHES <= "0001000000010001";
             wait;
         end process;
     end Behavioral;

- Run a behavioral simulation to verify the ALU's operation.
- Use the simulator's features to zoom, navigate, and inspect signal values.

#### 5. **Personalizing the ALU to Your Student ID**
- Determine the opcodes based on the last digit of your student ID using the provided table.
- Example for ID ending in 2:
- `num1 + num2`: Opcode 1
- `num1 - num2`: Opcode 15
- `num2 - num1`: Opcode 3
- etc.
- Implement logic to handle unrecognized opcodes by outputting zero.

#### 6. **Uploading Your Final Result**
- Upload your final code and a simulation showing the correct operation of your personalized ALU to the Canvas assignment for Lab 2.
- Ensure the simulation demonstrates the effect of each opcode with `num1 = 0100` and `num2 = 0011`.
- Save your final project on your U: drive for accessibility and safety.

By following these steps, you will complete the lab assignment effectively and ensure that your ALU is fully functional and personalized according to your student ID.