用verilog 编写一段SPI程序

以下是一个简单的SPI程序的Verilog代码示例：

module spi_master (
  input clk,
  input rst,
  output reg cs,
  output reg mosi,
  input miso,
  input sck,
  input [7:0] data_in,
  output [7:0] data_out,
  input [7:0] addr,
  input write,
  input read
);

  // 定义状态机状态
  localparam [2:0] IDLE = 3'b000;
  localparam [2:0] ADDRESS = 3'b001;
  localparam [2:0] WRITE = 3'b010;
  localparam [2:0] READ = 3'b011;
  localparam [2:0] DONE = 3'b100;

  // 定义状态机信号
  reg [2:0] state;
  reg [7:0] counter;
  reg [7:0] tx_data;
  reg [7:0] rx_data;

  // 初始化状态机
  always @(posedge clk, posedge rst) begin
    if (rst) begin
      state <= IDLE;
      cs <= 1'b1;
      mosi <= 1'b0;
      counter <= 8'd0;
      tx_data <= 8'd0;
      rx_data <= 8'd0;
    end else begin
      case (state)
        IDLE: begin
          if (write && !read) begin
            state <= ADDRESS;
            cs <= 1'b0;
            mosi <= 1'b0;
            tx_data <= addr;
          end else if (!write && read) begin
            state <= ADDRESS;
            cs <= 1'b0;
            mosi <= 1'b1;
            tx_data <= addr;
          end
        end
        ADDRESS: begin
          mosi <= tx_data[7];
          tx_data <= {tx_data[6:0], 1'b0};
          counter <= counter + 1;
          if (counter == 8) begin
            counter <= 8'd0;
            if (write) begin
              state <= WRITE;
              tx_data <= data_in;
            end else if (read) begin
              state <= READ;
              tx_data <= 8'd0;
            end
          end
        end
        WRITE: begin
          mosi <= tx_data[7];
          tx_data <= {tx_data[6:0], 1'b0};
          counter <= counter + 1;
          if (counter == 8) begin
            state <= IDLE;
            cs <= 1'b1;
            mosi <= 1'b0;
            counter <= 8'd0;
            tx_data <= 8'd0;
          end
        end
        READ: begin
          mosi <= 1'b1;
          rx_data <= {rx_data[6:0], miso};
          counter <= counter + 1;
          if (counter == 8) begin
            state <= DONE;
            cs <= 1'b1;
            mosi <= 1'b0;
            counter <= 8'd0;
            tx_data <= 8'd0;
          end
        end
        DONE: begin
          data_out <= rx_data;
          state <= IDLE;
          cs <= 1'b1;
          mosi <= 1'b0;
          counter <= 8'd0;
          tx_data <= 8'd0;
          rx_data <= 8'd0;
        end
      endcase
    end
  end

endmodule

在上述代码中，我们定义了一个SPI主机模块，它可以与SPI从机通信。该模块包含了一个状态机，它可以控制SPI通信的时序，并实现SPI的读写操作。我们可以根据需要修改这个模块来适应特定的应用场景。