module full_add(a,b,cin,sum,cout); input a,b,cin; output sum,cout; assign{cout,sum}=a+b+cin; endmodule 用verilog语言写出testbench代码

下面是一个简单的testbench代码，用于测试full_add模块：

module testbench;

reg a, b, cin;
wire sum, cout;

// Instantiate the full_add module
full_add full_add_inst(.a(a), .b(b), .cin(cin), .sum(sum), .cout(cout));

// Clock signal
reg clk = 0;

// Stimulus generation
initial begin
    // Test case 1: a=0, b=0, cin=0
    a = 0; b = 0; cin = 0;
    #10 $display("Test case 1: a=%b, b=%b, cin=%b", a, b, cin);
    #10 $display("sum=%b, cout=%b", sum, cout);

    // Test case 2: a=1, b=0, cin=1
    a = 1; b = 0; cin = 1;
    #10 $display("Test case 2: a=%b, b=%b, cin=%b", a, b, cin);
    #10 $display("sum=%b, cout=%b", sum, cout);

    // Test case 3: a=1, b=1, cin=0
    a = 1; b = 1; cin = 0;
    #10 $display("Test case 3: a=%b, b=%b, cin=%b", a, b, cin);
    #10 $display("sum=%b, cout=%b", sum, cout);

    // Test case 4: a=1, b=1, cin=1
    a = 1; b = 1; cin = 1;
    #10 $display("Test case 4: a=%b, b=%b, cin=%b", a, b, cin);
    #10 $display("sum=%b, cout=%b", sum, cout);

    // End testbench after all test cases have been executed
    #10 $finish;
end

// Clock generation
always #5 clk = ~clk;

endmodule

在这个testbench中，我们实例化了full_add模块，并通过四个测试用例对其进行测试。每个测试用例设置了不同的输入值，并在计算完成后打印出输出值。最后，我们使用$finish结束了testbench。