vivado导出pin delay

要导出Vivado中的pin delay，可以按照以下步骤进行操作：

1. 打开Vivado软件并创建一个空工程。
2. 进入控制台界面(tcl console)。
3. 使用命令"link_design -part FPGA型号"，例如"link_design -part xc7k325tffg900-2"，该命令将进入synthesized design界面。控制台将提示"link_design completed successfully"，表示链接成功。
4. 使用命令"write_csv pindelay.csv"，该命令将导出pin delay数据。
5. 根据控制台提示的目录，找到导出的pindelay.csv文件。

如果需要导出其他FPGA型号的pin delay，可以根据需求更改"link_design -part FPGA型号"命令中的FPGA型号参数，例如"link_design -part xc7vx690tffg1761-2"。<span class="em">1</span><span class="em">2</span><span class="em">3</span>
#### 引用[.reference_title]
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