循环可逆计数器的VHDL代码

循环可逆计数器是一种在数字电路中常用的计数器设计，它可以实现循环计数并且可以逆向计数。下面是一个简单的循环可逆计数器的VHDL代码示例：

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Reversible_Counter is
    generic (
        WIDTH : positive := 4
    );
    port (
        clk : in std_logic;
        reset : in std_logic;
        count : out unsigned(WIDTH-1 downto 0);
        direction : in std_logic
    );
end entity Reversible_Counter;

architecture Behavioral of Reversible_Counter is
    signal counter : unsigned(WIDTH-1 downto 0);
begin
    process(clk, reset)
    begin
        if reset = '1' then
            counter <= (others => '0');
        elsif rising_edge(clk) then
            if direction = '0' then
                counter <= counter + 1;
            else
                counter <= counter - 1;
            end if;
        end if;
    end process;

    count <= counter;
end architecture Behavioral;

上述代码中，`WIDTH`是计数器的位宽，`clk`是时钟信号，`reset`是复位信号，`count`是输出的计数值，`direction`是控制计数方向的信号。