写一个verilog状态机

以下是一个简单的Verilog状态机，它有两个状态：state1和state2。当输入信号为1时，状态机从state1转移到state2，当输入信号为0时，状态机从state2转移到state1。

module state_machine(
  input clk,
  input reset,
  input in,
  output reg out
);

  //定义状态
  localparam state1 = 1'b0;
  localparam state2 = 1'b1;

  //定义状态寄存器和下一个状态变量
  reg [1:0] state_reg, next_state;

  //定义状态转移条件
  always @(state_reg or in) begin
    case (state_reg)
      state1: begin
        if (in == 1) begin
          next_state = state2;
        end else begin
          next_state = state1;
        end
      end
      state2: begin
        if (in == 0) begin
          next_state = state1;
        end else begin
          next_state = state2;
        end
      end
      default: next_state = state1;
    endcase
  end

  //定义状态寄存器和输出信号
  always @(posedge clk, posedge reset) begin
    if (reset) begin
      state_reg <= state1;
      out <= 0;
    end else begin
      state_reg <= next_state;
      if (state_reg == state2) begin
        out <= 1;
      end else begin
        out <= 0;
      end
    end
  end

endmodule