给这段代码每一句话加上注释解释下列代码 module yujia ( input clk , input rst_n , input signed [8:0] shift_buf0 , input signed [8:0] shift_buf1 , input signed [8:0] shift_buf2 , input signed [8:0] shift_buf3 , input signed [8:0] shift_buf4 , input signed [8:0] shift_buf5 , input signed [8:0] shift_buf6 , input signed [8:0] shift_buf7 , input signed [8:0] shift_buf8 , output reg signed [9:0] add_0_8 , output reg signed [9:0] add_1_7 , output reg signed [9:0] add_2_6 , output reg signed [9:0] add_3_5 ); always @(posedge clk or negedge rst_n) begin if (!rst_n) begin add_0_8 <= 0 ; add_1_7 <= 0 ; add_2_6 <= 0 ; add_3_5 <= 0 ; end else begin add_0_8 <= shift_buf0 + shift_buf8 ; add_1_7 <= shift_buf1 + shift_buf7 ; add_2_6 <= shift_buf2 + shift_buf6 ; add_3_5 <= shift_buf3 + shift_buf5 ; end end endmodule

module yujia (
    input clk, // 时钟信号
    input rst_n, // 复位信号，低电平有效
    input signed [8:0] shift_buf0, // 输入数据，有符号，9位宽
    input signed [8:0] shift_buf1,
    input signed [8:0] shift_buf2,
    input signed [8:0] shift_buf3,
    input signed [8:0] shift_buf4,
    input signed [8:0] shift_buf5,
    input signed [8:0] shift_buf6,
    input signed [8:0] shift_buf7,
    input signed [8:0] shift_buf8,
    output reg signed [9:0] add_0_8, // 输出数据，有符号，10位宽
    output reg signed [9:0] add_1_7,
    output reg signed [9:0] add_2_6,
    output reg signed [9:0] add_3_5
);
always @(posedge clk or negedge rst_n) begin // 在时钟上升沿或复位信号下降沿时执行
    if (!rst_n) begin // 复位信号为低电平时
        add_0_8 <= 0; // 输出数据清零
        add_1_7 <= 0;
        add_2_6 <= 0;
        add_3_5 <= 0;
    end else begin // 复位信号为高电平时
        add_0_8 <= shift_buf0 + shift_buf8; // 输出数据等于输入数据之和
        add_1_7 <= shift_buf1 + shift_buf7;
        add_2_6 <= shift_buf2 + shift_buf6;
        add_3_5 <= shift_buf3 + shift_buf5;
    end
end
endmodule

该代码是一个Verilog模块，输入9个有符号的8位宽数据，通过加法器将第0个和第8个、第1个和第7个、第2个和第6个、第3个和第5个数据相加，并将结果作为4个有符号的10位宽输出数据。当复位信号为低电平时，输出数据清零。在时钟上升沿或复位信号下降沿时执行。