用verilog语言编写三变量多数表决器并写出相应的testbench测试文件

在Verilog语言中，编写一个三变量多数表决器（Majority Gate）通常会包含三个输入（A、B、C），一个输出Y，表示其中多数输入为高电平时的结果。以下是简化的三变量多数表决器的Verilog代码：

module majority_gate(
    input wire A, B, C,
    output wire Y
);
    always @* begin
        if((A && !B && !C) || (!A && B && !C) || (!A && !B && C)) // XOR of inputs
            Y = 1;
        else
            Y = 0; // Otherwise, Y is complement of the XOR result
    end
endmodule

接下来是针对这个模块的testbench测试文件，用于验证其功能是否正常：

// Test bench for the Majority Gate module
module majority_gate_tb;

reg [1:0] A, B, C; // Three input bits
wire Y; // Output bit from the gate

majority_gate maj_gate(A, B, C, Y);

initial begin
    $display("Testing with (A, B, C):", A, B, C);
    
    // Test cases:
    A = 0; B = 0; C = 0; // All low -> Y = 0 (Majority is 0)
    #10; $display("Case 1: Y = %b", Y); // Expect Y to be 0

    A = 0; B = 0; C = 1; // Two lows and one high -> Y = ? (Majority is 1)
    #10; $display("Case 2: Y = %b", Y);

    A = 1; B = 1; C = 0; // Two highs and one low -> Y = 1 (Majority is 2)
    #10; $display("Case 3: Y = %b", Y);

    // Add more test cases as needed
    
    #50; $finish; // End simulation after a while
end

endmodule