代码改错将out4延时从250000改为1500module clk_gen( input clk_in, // 杈撳叆绯荤粺鏃堕挓50MHz input rst_n, //绯荤粺澶嶄綅 output reg clk_out1, // 杈撳嚭50MHz鍒嗛涓?2MHz鐨勬椂閽熶俊鍙? output clk_out2, // 杈撳嚭棰戠巼銆佸崰绌烘瘮鍙皟鐨勫垎棰戞椂閽熶俊鍙? output clk_out3, output clk_out4 ); // 鏃堕挓鍒嗛鍣?1锛氬皢50MHz鍒嗛涓?2MHz reg [4:0] cnt1; wire clk_new; always@(posedge clk_in or negedge rst_n) begin if(!rst_n) begin cnt1 <= 5'd0; clk_out1 <= 1'b0; end else begin if(cnt1 == 5'd25-1) begin clk_out1 <= ~clk_out1; cnt1 <= 5'd0; end else begin clk_out1 <= clk_out1; cnt1 <= cnt1 + 1; end end end reg clk_out2r; assign clk_new = clk_out1; reg [5:0] cntr; parameter N = 6'd50; //------------------- always@(posedge clk_new or negedge rst_n) begin if(!rst_n) cntr <= 6'd0; else if(cntr == N-1) cntr <= 6'd0; else cntr <= cntr + 1'b1; end always@(posedge clk_new or negedge rst_n) begin if(!rst_n) clk_out2r <= 1'b0; else begin if(cntr <= 6'd4) // 0到2 三个高电平时钟脉冲 //---------------------- clk_out2r <= 1'b1; else if(cntr > 6'd4 && cntr <= N-1) // 3到4 二个低电平时钟脉冲 clk_out2r <= 1'b0; else clk_out2r <=clk_out2r; end end assign clk_out2 = clk_out2r; assign clk_out3 = clk_new & clk_out2r; reg [17:0] cnt_5ms; always@(posedge clk_in or negedge rst_n) begin if(!rst_n) cnt_5ms <= 18'd0; else if(cnt_5ms == 18'd249_999) cnt_5ms <= cnt_5ms; else cnt_5ms <= cnt_5ms + 1'b1; end assign clk_out4 = (cnt_5ms == 18'd249_999)?clk_out2r:1'b0; // 鏃堕挓鍒嗛鍣?2锛氶鐜囥?佸崰绌烘瘮鍙皟鐨勫垎棰戞椂閽? //瀹氫箟璁℃暟鍣ㄧ殑浣嶅,$clog2()涓哄彇瀵规暟鎿嶄綔锛屽湪缂栬瘧杩囩▼涓墽琛屽畬鎴愩?傚洜姝ゅ湪妯″潡杩愯杩囩▼涓瑿NT_WIDTH鏄竴涓‘瀹氱殑鏁板?笺?? endmodule

在这个代码中，clk_out4是一个延时为250000个时钟周期的时钟信号。要将其延时改为1500个时钟周期，只需要将cnt_5ms的计数值从18'd249_999改为18'd1499即可。修改后的代码如下：

module clk_gen(
    input clk_in, // 输入系统时钟频率50MHz
    input rst_n, //系统复位
    output reg clk_out1, // 输出50MHz时钟的2MHz的时钟周期的节拍信号
    output clk_out2, // 输出时钟频率，以及调用时钟节拍的时钟周期的节拍信号
    output clk_out3, // 与时钟节拍相乘的时钟节拍信号
    output clk_out4 // 时钟信号
);

    reg [4:0] cnt1; 
    wire clk_new;

    // 产生2MHz的时钟节拍信号
    always@(posedge clk_in or negedge rst_n) begin
        if(!rst_n) begin
            cnt1 <= 5'd0;
            clk_out1 <= 1'b0;
        end else begin
            if(cnt1 == 5'd25-1) begin
                clk_out1 <= ~clk_out1;
                cnt1 <= 5'd0;
            end else begin
                clk_out1 <= clk_out1;
                cnt1 <= cnt1 + 1;
            end
        end
    end

    reg clk_out2r;
    assign clk_new = clk_out1;
    reg [5:0] cntr;
    parameter N = 6'd50;

    // 产生时钟频率，以及调用时钟节拍的时钟周期的节拍信号
    always@(posedge clk_new or negedge rst_n) begin
        if(!rst_n) cntr <= 6'd0;
        else if(cntr == N-1) cntr <= 6'd0;
        else cntr <= cntr + 1'b1;
    end

    always@(posedge clk_new or negedge rst_n) begin
        if(!rst_n) clk_out2r <= 1'b0;
        else begin
            if(cntr <= 6'd4) // 0到2 三个高电平时钟脉冲
                clk_out2r <= 1'b1;
            else if(cntr > 6'd4 && cntr <= N-1) // 3到4 二个低电平时钟脉冲
                clk_out2r <= 1'b0;
            else
                clk_out2r <=clk_out2r;
        end
    end
    assign clk_out2 = clk_out2r;

    // 产生与时钟节拍相乘的时钟节拍信号
    assign clk_out3 = clk_new & clk_out2r;

    // 产生延时为1500个时钟周期的时钟信号
    reg [17:0] cnt_5ms;
    always@(posedge clk_in or negedge rst_n) begin
        if(!rst_n) cnt_5ms <= 18'd0;
        else if(cnt_5ms == 18'd1499) cnt_5ms <= cnt_5ms;
        else cnt_5ms <= cnt_5ms + 1'b1;
    end
    assign clk_out4 = (cnt_5ms == 18'd1499)?clk_out2r:1'b0;
endmodule