用verilog写riscv五级流水线架构

以下是一个简单的 RISC-V 五级流水线处理器的 Verilog 实现，包括 Fetch、Decode、Execute、Memory 和 Writeback 阶段。

module riscv_pipeline(
  input clk, reset,
  input [31:0] instruction_in,
  input [31:0] data_in,
  output [31:0] data_out
);

// 定义寄存器文件，共 32 个 32 位寄存器
reg [31:0] reg_file [0:31];
initial for (int i = 0; i < 32; i = i + 1)
  reg_file[i] = 0;

// 定义 PC 寄存器，存放下一条指令的地址
reg [31:0] pc;
initial pc = 0;

// 定义流水线寄存器
reg [31:0] pc_reg;
reg [31:0] instruction_reg;
reg [31:0] rs1_reg;
reg [31:0] rs2_reg;
reg [31:0] rd_reg;
reg [31:0] alu_result_reg;
reg [1:0]  alu_ctrl_reg;
reg [1:0]  mem_ctrl_reg;
reg [31:0] data_reg;
reg [31:0] branch_target_reg;

// 定义控制信号
reg [6:0] opcode;
reg [2:0] funct3;
reg [6:0] funct7;
reg [3:0] rs1;
reg [3:0] rs2;
reg [3:0] rd;
reg [31:0] imm;
reg       alu_src;
reg       branch;
reg       mem_read;
reg       mem_write;
reg [1:0]  mem_width;
reg       reg_write;

// Fetch 阶段
assign instruction_reg = instruction_in;
assign pc_reg = pc;
always @(posedge clk)
begin
  if (reset)
    pc <= 0;
  else if (branch)
    pc <= branch_target_reg;
  else
    pc <= pc + 4;
end

// Decode 阶段
assign opcode = instruction_reg[6:0];
assign funct3 = instruction_reg[14:12];
assign funct7 = instruction_reg[31:25];
assign rs1 = instruction_reg[19:15];
assign rs2 = instruction_reg[24:20];
assign rd = instruction_reg[11:7];
always @(posedge clk)
begin
  rs1_reg <= reg_file[rs1];
  rs2_reg <= reg_file[rs2];
  rd_reg <= rd;
  imm <= { {20{instruction_reg[31]}}, instruction_reg[31:20] };
  case (opcode)
    7'd3: // I-type
      alu_src <= 1'b1;
      mem_width <= 2'b00;
      funct3 {
        3'd0: alu_ctrl_reg <= 2'b00; // ADD
        3'd1: alu_ctrl_reg <= 2'b01; // SLL
        3'd2: alu_ctrl_reg <= 2'b10; // SLT
        3'd3: alu_ctrl_reg <= 2'b11; // SLTU
        3'd4: alu_ctrl_reg <= 2'b01; // XOR
        3'd5: alu_ctrl_reg <= 2'b00; // SRL
        3'd6: alu_ctrl_reg <= 2'b10; // OR
        3'd7: alu_ctrl_reg <= 2'b11; // AND
      }
    7'd19: // U-type
      alu_src <= 1'b0;
      mem_width <= 2'b00;
      alu_ctrl_reg <= 2'b00; // ADD
    7'd103: // J-type
      alu_src <= 1'b0;
      mem_width <= 2'b00;
      alu_ctrl_reg <= 2'b00; // ADD
    7'd35: // S-type
      alu_src <= 1'b1;
      mem_width <= 2'b01;
      mem_write <= 1'b1;
      funct3 {
        3'd0: alu_ctrl_reg <= 2'b00; // ADD
        3'd1: alu_ctrl_reg <= 2'b01; // SLL
        3'd2: alu_ctrl_reg <= 2'b10; // SLT
        3'd3: alu_ctrl_reg <= 2'b11; // SLTU
        3'd4: alu_ctrl_reg <= 2'b01; // XOR
        3'd5: alu_ctrl_reg <= 2'b00; // SRL
        3'd6: alu_ctrl_reg <= 2'b10; // OR
        3'd7: alu_ctrl_reg <= 2'b11; // AND
      }
    7'd99: // B-type
      alu_src <= 1'b1;
      mem_width <= 2'b00;
      branch <= 1'b1;
      case (funct3)
        3'd0: alu_ctrl_reg <= 2'b01; // BEQ
        3'd1: alu_ctrl_reg <= 2'b10; // BNE
        3'd4: alu_ctrl_reg <= 2'b11; // BLT
        3'd5: alu_ctrl_reg <= 2'b11; // BGE
        3'd6: alu_ctrl_reg <= 2'b10; // BLTU
        3'd7: alu_ctrl_reg <= 2'b10; // BGEU
      endcase
  endcase
end

// Execute 阶段
always @(posedge clk)
begin
  case (alu_ctrl_reg)
    2'b00: alu_result_reg <= rs1_reg + rs2_reg; // ADD
    2'b01: alu_result_reg <= rs1_reg << rs2_reg; // SLL
    2'b10: alu_result_reg <= (rs1_reg < rs2_reg) ? 1 : 0; // SLT
    2'b11: alu_result_reg <= (rs1_reg < rs2_reg) ? 1 : 0; // SLTU
  endcase
end

// Memory 阶段
always @(posedge clk)
begin
  if (mem_read)
    data_reg <= data_in;
  else if (mem_write)
    data_reg <= rs2_reg;
end

// Writeback 阶段
always @(posedge clk)
begin
  if (reg_write)
    reg_file[rd_reg] <= alu_result_reg;
end

// 计算分支目标地址
assign branch_target_reg = pc + imm;

// 输出结果
assign data_out = data_reg;

endmodule

需要注意的是，这只是一个简单的实现，没有考虑多周期指令、数据冒险、控制冒险等问题。在实际应用中，需要进行更加细致的设计和优化。