module bubble_sort(clock, reset_n, input_vector, output_vector);input clock, reset_n;input [3:0] input_vector [9:0];output [3:0] output_vector [9:0];reg [3:0] temp;reg [3:0] temp_vector [9:0];always @(posedge clock or negedge reset_n)begin if(!reset_n) begin temp_vector <= 10'd0; // 初始化输出向量为 0 end else begin temp_vector <= input_vector; // 将输入向量复制到暂存向量中以进行排序 for(int i = 0; i < 9; i = i+1) begin for(int j = i+1; j < 10; j = j+1) begin if(temp_vector[i] > temp_vector[j]) begin temp = temp_vector[i]; temp_vector[i] = temp_vector[j]; temp_vector[j] = temp; end end end output_vector <= temp_vector; // 将排序后的向量赋值到输出向量中 endendendmodule 请给这段代码在quartus中写一个测试代码

// Test code for bubble_sort module

module bubble_sort_test();

// Inputs
reg clock = 0;
reg reset_n = 0;
reg [3:0] input_vector [9:0];

// Outputs
wire [3:0] output_vector [9:0];

// Instantiate the DUT
bubble_sort dut (
.clock(clock),
.reset_n(reset_n),
.input_vector(input_vector),
.output_vector(output_vector)
);

// Generate clock
always #10 clock = ~clock;

// Initialize input vector
initial begin
input_vector <= {4'b1100, 4'b0011, 4'b1010, 4'b0110, 4'b0101, 4'b1000, 4'b1111, 4'b0000, 4'b1101, 4'b0010};
#100 reset_n = 1;
end

// Wait a few clock cycles before checking the output
initial #500 $finish;

endmodule