verilog实现将下变频后的15位的IQ分别经过鉴相器计算误差信号，再通过环路滤波器来输出32位DDS的频率控制字的costas环

module costas (clk, reset, in_i, in_q, out_freq);

input clk, reset;
input [14:0] in_i, in_q;
output reg signed [31:0] out_freq;

reg signed [14:0] phase_err;
reg signed [14:0] old_phase_err;
reg signed [14:0] integrator;
reg signed [14:0] old_integrator;
reg signed [14:0] proportional;
reg signed [14:0] old_proportional;
reg signed [14:0] loop_filter;
reg signed [14:0] old_loop_filter;

parameter Kp = 5'b10000; // Proportional gain
parameter Ki = 5'b00010; // Integral gain
parameter Kf = 5'b01000; // Loop filter gain

// Phase detector
always @(posedge clk) begin
old_phase_err <= phase_err;
phase_err <= in_i * in_q;
end

// Integrator
always @(posedge clk) begin
old_integrator <= integrator;
integrator <= old_integrator + Ki * phase_err;
end

// Proportional
always @(posedge clk) begin
old_proportional <= proportional;
proportional <= Kp * phase_err;
end

// Loop filter
always @(posedge clk) begin
old_loop_filter <= loop_filter;
loop_filter <= Kf * (proportional + integrator);
end

// Frequency control
always @(posedge clk) begin
out_freq <= out_freq + loop_filter;
end

endmodule