给我5个systemverilog .sv文件，文件大小5-10k

以下是5个SystemVerilog .sv文件，每个文件大小在5-10k之间：

1. fifo.sv：

module fifo(
  input clk, rst_n, wr_en, rd_en,
  input [7:0] data_in,
  output reg [7:0] data_out,
  output reg empty, full
);

parameter DEPTH = 16;

reg [7:0] ram [DEPTH-1:0];
reg [3:0] wr_ptr, rd_ptr;
reg [4:0] count;

always @(posedge clk or negedge rst_n) begin
  if (!rst_n) begin
    wr_ptr <= 0;
    rd_ptr <= 0;
    count <= 0;
    empty <= 1;
    full <= 0;
  end else begin
    if (wr_en && !full) begin
      ram[wr_ptr] <= data_in;
      wr_ptr <= wr_ptr + 1;
      count <= count + 1;
      empty <= 0;
      if (count == DEPTH) full <= 1;
    end
    if (rd_en && !empty) begin
      data_out <= ram[rd_ptr];
      rd_ptr <= rd_ptr + 1;
      count <= count - 1;
      full <= 0;
      if (count == 1) empty <= 1;
    end
  end
end

endmodule

2. full_adder.sv：

module full_adder(
  input a, b, cin,
  output sum, cout
);

assign s = a ^ b ^ cin;
assign c = (a & b) | (a & cin) | (b & cin);

endmodule

3. counter.sv：

module counter(
  input clk, rst_n,
  output reg [7:0] count
);

always @(posedge clk or negedge rst_n) begin
  if (!rst_n) count <= 0;
  else count <= count + 1;
end

endmodule

4. uart_rx.sv：

module uart_rx(
  input clk, rst_n, rx,
  output reg [7:0] data_out,
  output reg data_valid
);

parameter BAUD_RATE = 9600;

reg [7:0] shift_reg;
reg [3:0] bit_count;
reg start_bit_detected, stop_bit_detected, data_ready;

always @(posedge clk or negedge rst_n) begin
  if (!rst_n) begin
    shift_reg <= 0;
    bit_count <= 0;
    start_bit_detected <= 0;
    stop_bit_detected <= 0;
    data_ready <= 0;
    data_valid <= 0;
  end else begin
    if (!start_bit_detected && !rx) begin
      start_bit_detected <= 1;
      bit_count <= 0;
    end else if (start_bit_detected && bit_count < 8) begin
      bit_count <= bit_count + 1;
      shift_reg <= {shift_reg[6:0], rx};
    end else if (bit_count == 8) begin
      stop_bit_detected <= rx;
      data_ready <= 1;
    end
    if (stop_bit_detected && data_ready) begin
      data_out <= shift_reg;
      data_ready <= 0;
      data_valid <= 1;
      start_bit_detected <= 0;
      stop_bit_detected <= 0;
      bit_count <= 0;
    end
  end
end

endmodule

5. spi_master.sv：

module spi_master(
  input clk, rst_n, cs_n, sclk, mosi,
  output reg miso
);

parameter DELAY = 100;

reg [7:0] tx_data;
reg [7:0] rx_data;
reg [3:0] bit_count;
reg [7:0] shift_reg;
reg [7:0] rx_shift_reg;
reg cs_n_prev, sclk_prev;
reg tx_done, rx_done;

always @(posedge clk or negedge rst_n) begin
  if (!rst_n) begin
    tx_data <= 0;
    rx_data <= 0;
    bit_count <= 0;
    shift_reg <= 0;
    rx_shift_reg <= 0;
    cs_n_prev <= 1;
    sclk_prev <= 1;
    miso <= 1;
    tx_done <= 1;
    rx_done <= 1;
  end else begin
    if (cs_n_prev && !cs_n) begin
      tx_done <= 0;
      rx_done <= 0;
      bit_count <= 0;
      shift_reg <= tx_data;
      rx_shift_reg <= 0;
      miso <= 1;
    end else if (!cs_n_prev && cs_n) begin
      tx_done <= 1;
      rx_done <= 1;
      rx_data <= rx_shift_reg;
    end
    if (!tx_done && !sclk_prev && sclk) begin
      shift_reg <= {shift_reg[6:0], 0};
      bit_count <= bit_count + 1;
      if (bit_count == 7) begin
        shift_reg <= {shift_reg[6:0], mosi};
        bit_count <= bit_count + 1;
      end
      if (bit_count == 8) begin
        bit_count <= 0;
        tx_done <= 1;
      end
    end
    if (!rx_done && sclk_prev && !sclk) begin
      rx_shift_reg <= {rx_shift_reg[6:0], miso};
      bit_count <= bit_count + 1;
      if (bit_count == 8) begin
        bit_count <= 0;
        rx_done <= 1;
      end
    end
    if (!cs_n && tx_done && !rx_done && (sclk_prev == 1)) begin
      miso <= shift_reg[7];
    end
    cs_n_prev <= cs_n;
    sclk_prev <= sclk;
  end
end

endmodule