用RTL级描述对单稳态电路进行Verilog HDL建模,画出电路结构图

以下是单稳态电路的Verilog HDL代码及电路结构图：

module monostable(input trigger, output reg out, parameter delay = 10);
    reg state;
    integer count;
    
    always @(posedge trigger)
        begin
            state <= 1'b1;
            count <= delay;
        end
    
    always @(posedge clk)
        begin
            if (count > 0)
                count <= count - 1;
            if (count == 0)
                begin
                    state <= 1'b0;
                    out <= 1'b1;
                end
            else
                out <= 1'b0;
        end
endmodule

电路结构图如下：