八位七段数码管动态显示电路的设计 设计原理 段选:数码管的中的那一个段被输入有效电平,则相应的这一段被点亮。反之则不亮。 位选:八个数码管的a、b、c、d、e、f、g、h、dp都连在了一起,分别由各自的位选信号来控制,被选通的数码管显示数据,其余关闭。 设计内容 在时钟信号的作用下,通过输入的键值在数码管上显示相应的键值。用四个拨动开关做为输入,当四个拨动开关置为一个二进制数时,在数码管上显示其十六进制的值。以上述要求写一段可以正常运行的VHDL代码
时间: 2024-03-07 10:47:38 浏览: 114
实验四八位七段数码管动态显示电路的设计.pdf
以下是一个基于FPGA的八位七段数码管动态显示电路的VHDL设计代码,它可以根据输入的四个开关的二进制值来在数码管上显示相应的十六进制值:
```vhdl
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity num_display is
Port ( clk : in STD_LOGIC;
sw : in STD_LOGIC_VECTOR(3 downto 0);
seg : out STD_LOGIC_VECTOR(6 downto 0);
dig : out STD_LOGIC_VECTOR(7 downto 0));
end num_display;
architecture Behavioral of num_display is
signal counter : integer range 0 to 4999999 := 0;
--数码管段选信号
signal seg_o : STD_LOGIC_VECTOR(6 downto 0);
--数码管位选信号
signal dig_o : STD_LOGIC_VECTOR(7 downto 0);
--数码管显示的十六进制数值
signal hex_num : STD_LOGIC_VECTOR(3 downto 0);
--数码管显示的二进制值
signal bin_num : STD_LOGIC_VECTOR(15 downto 0);
begin
--将四个开关的二进制值转换为十六进制数值
hex_num <= conv_std_logic_vector(conv_integer(sw), 4);
--将十六进制数值转换为二进制值
bin_num <= std_logic_vector(to_unsigned(to_integer(unsigned(hex_num)), 16));
--数码管的段选信号
seg_o <= "0000001" when bin_num(3 downto 0) = "0000" else
"1001111" when bin_num(3 downto 0) = "0001" else
"0010010" when bin_num(3 downto 0) = "0010" else
"0000110" when bin_num(3 downto 0) = "0011" else
"1001100" when bin_num(3 downto 0) = "0100" else
"0100100" when bin_num(3 downto 0) = "0101" else
"0100000" when bin_num(3 downto 0) = "0110" else
"0001111" when bin_num(3 downto 0) = "0111" else
"0000000" when bin_num(3 downto 0) = "1000" else
"0000100" when bin_num(3 downto 0) = "1001" else
"0001000" when bin_num(3 downto 0) = "1010" else
"1100000" when bin_num(3 downto 0) = "1011" else
"0110001" when bin_num(3 downto 0) = "1100" else
"1000010" when bin_num(3 downto 0) = "1101" else
"0110000" when bin_num(3 downto 0) = "1110" else
"0111000";
--数码管的位选信号
dig_o <= "11111110" when counter = 0 else
"11111101" when counter = 1 else
"11111011" when counter = 2 else
"11110111" when counter = 3 else
"11101111" when counter = 4 else
"11011111" when counter = 5 else
"10111111" when counter = 6 else
"01111111" when counter = 7 else
"11111110";
--连接段选信号和位选信号
seg <= seg_o;
dig <= dig_o;
--时钟计数器
process(clk)
begin
if rising_edge(clk) then
if counter = 7 then
counter <= 0;
else
counter <= counter + 1;
end if;
end if;
end process;
end Behavioral;
```
这段代码中,使用了一个时钟计数器来控制数码管的位选信号,计数器的值从0到7,分别对应八个数码管的位选信号。通过选择不同的位选信号,可以控制哪一个数码管显示数据。而段选信号则是根据输入的键值来确定,使用了一个简单的逻辑表达式来实现。
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