vivado8位数码管位选控制代码
时间: 2023-11-26 19:45:49 浏览: 35
```verilog
module num_display(
input clk,
input [3:0] hex0,
input [3:0] hex1,
input [3:0] hex2,
input [3:0] hex3,
input dp_in,
output reg [7:0] anode
);
reg [26:0] cnt;
reg [2:0] sel;
always @(posedge clk) begin
if(cnt == 250000) begin
cnt <= 0; sel <= sel + 1;
case(sel)
3'd0: anode <= {dp_in, hex0};
3'd1: anode <= {dp_in, hex1};
3'd2: anode <= {dp_in, hex2};
3'd3: anode <= {dp_in, hex3};
default: anode <= 8'b11111111;
endcase
end
else begin
cnt <= cnt + 1;
end
end
endmodule
```