vhdl8-3编码器代码

下面是一个基于 VHDL 的 8-3 编码器代码示例：

library ieee;
use ieee.std_logic_1164.all;

entity encoder8_3 is
    port (
        input : in std_logic_vector(7 downto 0);
        output : out std_logic_vector(2 downto 0)
    );
end entity;

architecture behavioral of encoder8_3 is
begin
    process(input)
    begin
        case input is
            when "00000001" => output <= "000"; -- input = 1
            when "00000010" => output <= "001"; -- input = 2
            when "00000100" => output <= "010"; -- input = 4
            when "00001000" => output <= "011"; -- input = 8
            when "00010000" => output <= "100"; -- input = 16
            when "00100000" => output <= "101"; -- input = 32
            when "01000000" => output <= "110"; -- input = 64
            when "10000000" => output <= "111"; -- input = 128
            when others => output <= "000"; -- default
        end case;
    end process;
end architecture;

此编码器将 8 位输入编码为 3 位输出。如果输入为 1，则输出为 000，如果输入为 2，则输出为 001，以此类推。如果输入是其他值，则输出将为 000。