ifndef verilog
时间: 2023-10-26 08:23:11 浏览: 108
ifndef是Verilog语言中的条件编译指令,与
ifdef是相反的。当其后的标识符未被定义时,则编译后续的代码段。比如在Verilog代码中使用`ifndef verilog,当verilog这个标识符未被定义时,编译后续的代码。123
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- 1 2 [Verilog语法之条件编译指令
ifdef,
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