请给出实现以下逻辑的verilog代码：输入信号通过温度计码产生逻辑产生了8位的温度计码，经过8-3编码器生成3位的二进制码，在经过模8加法器生成三位的二进制指针，该指针通过寄存器寄存，由指针和输入的温度计码通过桶形移位器共同决定8位DWA算法的选择输出，通过输出码来决定选取的DAC单位元件，并给出另一段针对上述代码的可以使用vivado进行测试和仿真的的testbench代码

以下是实现上述逻辑的verilog代码：

module temperature_controller (
    input [7:0] temp_code,
    input clk,
    input rst,
    output reg [7:0] dac_out
);

reg [2:0] pointer;
reg [7:0] dwa_out;
reg [2:0] dwa_sel;

// 8-3编码器
always @ (temp_code) begin
    case(temp_code)
        8'b00000001: pointer <= 3'b000;
        8'b00000010: pointer <= 3'b001;
        8'b00000100: pointer <= 3'b010;
        8'b00001000: pointer <= 3'b011;
        8'b00010000: pointer <= 3'b100;
        8'b00100000: pointer <= 3'b101;
        8'b01000000: pointer <= 3'b110;
        8'b10000000: pointer <= 3'b111;
        default: pointer <= 3'b000;
    endcase
end

// 模8加法器
always @ (posedge clk, posedge rst) begin
    if (rst) begin
        dwa_sel <= 3'b000;
    end else begin
        dwa_sel <= (dwa_sel + pointer) % 8;
    end
end

// DWA算法选择逻辑
always @ (posedge clk, posedge rst) begin
    if (rst) begin
        dwa_out <= 8'd0;
    end else begin
        case(dwa_sel)
            3'b000: dwa_out <= (temp_code << 1);
            3'b001: dwa_out <= (temp_code << 2);
            3'b010: dwa_out <= (temp_code << 3);
            3'b011: dwa_out <= (temp_code << 4);
            3'b100: dwa_out <= (temp_code << 5);
            3'b101: dwa_out <= (temp_code << 6);
            3'b110: dwa_out <= (temp_code << 7);
            3'b111: dwa_out <= (temp_code << 8);
            default: dwa_out <= 8'd0;
        endcase
    end
end

// DAC单位元件选择逻辑
always @ (posedge clk, posedge rst) begin
    if (rst) begin
        dac_out <= 8'd0;
    end else begin
        case(dwa_sel)
            3'b000: dac_out <= dwa_out[7:0];
            3'b001: dac_out <= dwa_out[6:0];
            3'b010: dac_out <= dwa_out[5:0];
            3'b011: dac_out <= dwa_out[4:0];
            3'b100: dac_out <= dwa_out[3:0];
            3'b101: dac_out <= dwa_out[2:0];
            3'b110: dac_out <= dwa_out[1:0];
            3'b111: dac_out <= dwa_out[0];
            default: dac_out <= 8'd0;
        endcase
    end
end

endmodule

以下是针对上述verilog代码的testbench代码：

module temperature_controller_tb;

reg [7:0] temp_code;
reg clk;
reg rst;

wire [7:0] dac_out;

temperature_controller uut (
    .temp_code(temp_code),
    .clk(clk),
    .rst(rst),
    .dac_out(dac_out)
);

initial begin
    clk = 1;
    forever #5 clk = ~clk;
end

initial begin
    rst = 1;
    temp_code = 8'b00000001;
    #10 rst = 0;
    #100 temp_code = 8'b00000100;
    #100 temp_code = 8'b00100000;
    #100 temp_code = 8'b10000000;
    #100 $finish;
end

endmodule

在上述testbench代码中，我们设置了输入信号temp_code的值，并且通过时钟信号clk来驱动寄存器的更新，同时也设置了复位信号rst来进行系统的复位。最后，我们检查输出信号dac_out是否符合预期，来验证我们实现的verilog代码的正确性。