[DRC UCIO-1] Unconstrained Logical Port: 8 out of 139 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: USBIND_0_0_port_indctl[1:0], USBIND_0_0_vbus_pwrfault, USBIND_0_0_vbus_pwrselect, UART_0_0_rxd, UART_0_0_txd, FCLK_RESET0_N_0, and FCLK_CLK0_0.
时间: 2024-03-18 08:44:20 浏览: 113
这个问题看起来是一个警告信息,提示在设计中有一些逻辑端口没有指定物理引脚位置,可能会影响性能、信号完整性,甚至会导致设备损坏。为了纠正这个问题,需要指定所有的引脚位置。如果不想指定引脚位置,可以使用 set_property SEVERITY {Warning} [get_drc_checks UCIO-1] 命令生成位流文件,但这并不推荐。需要注意的是,对于使用 Vivado Runs 基础架构的设计,需要将这个命令添加到 .tcl 文件中,并将该文件作为 write_bitstream 步骤的前钩子。需要解决的逻辑端口包括 USBIND_0_0_port_indctl[1:0]、USBIND_0_0_vbus_pwrfault、USBIND_0_0_vbus_pwrselect、UART_0_0_rxd、UART_0_0_txd、FCLK_RESET0_N_0 和 FCLK_CLK0_0。