按照这个文件要求用verilog编写完整代码(基于basys3）

根据提供的文档，以下是实现该设计所需的Verilog代码。我们将逐步构建每个模块，并最终将它们连接在一起形成顶层模块。

### 1. 通用计数器模块 (`Generic_counter`)

module Generic_counter #(
    parameter COUNTER_WIDTH = 4,
    parameter COUNTER_MAX = 9
)(
    input wire CLK,
    input wire RESET,
    input wire ENABLE,
    output reg [COUNTER_WIDTH-1:0] COUNT,
    output reg TRIG_OUT
);

    always @(posedge CLK or posedge RESET) begin
        if (RESET) begin
            COUNT <= 0;
            TRIG_OUT <= 0;
        end else if (ENABLE) begin
            if (COUNT == COUNTER_MAX) begin
                COUNT <= 0;
                TRIG_OUT <= 1;
            end else begin
                COUNT <= COUNT + 1;
                TRIG_OUT <= 0;
            end
        end else begin
            TRIG_OUT <= 0;
        end
    end

endmodule

### 2. 四路多路复用器模块 (`Multiplexer`)

module Multiplexer (
    input wire [1:0] SEL,
    input wire [4:0] IN0, IN1, IN2, IN3,
    output reg [4:0] OUT
);

    always @(*) begin
        case (SEL)
            2'b00: OUT = IN0;
            2'b01: OUT = IN1;
            2'b10: OUT = IN2;
            2'b11: OUT = IN3;
            default: OUT = 5'b00000;
        endcase
    end

endmodule

### 3. 7段解码器模块 (`Seg7Decoder`)

假设我们已经有一个现成的 `Seg7Decoder` 模块：

module Seg7Decoder (
    input wire [4:0] BCD_IN,
    output reg [6:0] SEGMENT_OUT
);

    // 假设这里已经有实现
    // 这里只是示例，具体实现需要参考Basys 3 FPGA板手册
    always @(*) begin
        case (BCD_IN[3:0])
            4'b0000: SEGMENT_OUT = 7'b1000000; // 0
            4'b0001: SEGMENT_OUT = 7'b1111001; // 1
            4'b0010: SEGMENT_OUT = 7'b0100100; // 2
            4'b0011: SEGMENT_OUT = 7'b0110000; // 3
            4'b0100: SEGMENT_OUT = 7'b0011001; // 4
            4'b0101: SEGMENT_OUT = 7'b0010010; // 5
            4'b0110: SEGMENT_OUT = 7'b0000010; // 6
            4'b0111: SEGMENT_OUT = 7'b1111000; // 7
            4'b1000: SEGMENT_OUT = 7'b0000000; // 8
            4'b1001: SEGMENT_OUT = 7'b0010000; // 9
            default: SEGMENT_OUT = 7'b1111111; // Off
        endcase
        SEGMENT_OUT[6] = BCD_IN[4]; // 控制小数点
    end

endmodule

### 4. 顶层模块 (`Top_Module`)

module Top_Module (
    input wire CLK,
    input wire RESET,
    input wire ENABLE,
    output reg [3:0] SEG_SELECT,
    output reg [6:0] DEC_OUT
);

    // 信号声明
    wire [16:0] Count_17bit;
    wire Trig_17bit;
    wire [3:0] Count_4bit_0, Count_4bit_1, Count_4bit_2, Count_4bit_3;
    wire Trig_4bit_0, Trig_4bit_1, Trig_4bit_2, Trig_4bit_3;
    wire [4:0] Mux_In0, Mux_In1, Mux_In2, Mux_In3;
    wire [4:0] Mux_Out;

    // 实例化17位计数器
    Generic_counter #(.COUNTER_WIDTH(17), .COUNTER_MAX(99999)) Counter_17bit (
        .CLK(CLK),
        .RESET(RESET),
        .ENABLE(1'b1),
        .COUNT(Count_17bit),
        .TRIG_OUT(Trig_17bit)
    );

    // 实例化四个4位计数器
    Generic_counter Counter_4bit_0 (
        .CLK(CLK),
        .RESET(RESET),
        .ENABLE(Trig_17bit),
        .COUNT(Count_4bit_0),
        .TRIG_OUT(Trig_4bit_0)
    );

    Generic_counter Counter_4bit_1 (
        .CLK(CLK),
        .RESET(RESET),
        .ENABLE(Trig_4bit_0),
        .COUNT(Count_4bit_1),
        .TRIG_OUT(Trig_4bit_1)
    );

    Generic_counter Counter_4bit_2 (
        .CLK(CLK),
        .RESET(RESET),
        .ENABLE(Trig_4bit_1),
        .COUNT(Count_4bit_2),
        .TRIG_OUT(Trig_4bit_2)
    );

    Generic_counter Counter_4bit_3 (
        .CLK(CLK),
        .RESET(RESET),
        .ENABLE(Trig_4bit_2),
        .COUNT(Count_4bit_3),
        .TRIG_OUT(Trig_4bit_3)
    );

    // 实例化四路多路复用器
    assign Mux_In0 = {1'b1, Count_4bit_0};
    assign Mux_In1 = {1'b1, Count_4bit_1};
    assign Mux_In2 = {Count_4bit_2[3], Count_4bit_2[2:0]};
    assign Mux_In3 = {1'b1, Count_4bit_3};

    Multiplexer Mux (
        .SEL(SEG_SELECT),
        .IN0(Mux_In0),
        .IN1(Mux_In1),
        .IN2(Mux_In2),
        .IN3(Mux_In3),
        .OUT(Mux_Out)
    );

    // 实例化7段解码器
    Seg7Decoder Decoder (
        .BCD_IN(Mux_Out),
        .SEGMENT_OUT(DEC_OUT)
    );

    // 生成2位选择信号
    Generic_counter #(.COUNTER_WIDTH(2), .COUNTER_MAX(3)) Strobe_Counter (
        .CLK(CLK),
        .RESET(RESET),
        .ENABLE(1'b1),
        .COUNT(SEG_SELECT),
        .TRIG_OUT()
    );

endmodule

### 5. 约束文件 (`constraints.xdc`)

确保在约束文件中正确配置引脚映射：

set_property PACKAGE_PIN W5 [get_ports {CLK}]
set_property IOSTANDARD LVCMOS33 [get_ports {CLK}]

set_property PACKAGE_PIN V10 [get_ports {RESET}]
set_property IOSTANDARD LVCMOS33 [get_ports {RESET}]

set_property PACKAGE_PIN V9 [get_ports {ENABLE}]
set_property IOSTANDARD LVCMOS33 [get_ports {ENABLE}]

set_property PACKAGE_PIN G14 [get_ports {SEG_SELECT[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SEG_SELECT[0]}]

set_property PACKAGE_PIN H14 [get_ports {SEG_SELECT[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SEG_SELECT[1]}]

set_property PACKAGE_PIN K15 [get_ports {SEG_SELECT[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SEG_SELECT[2]}]

set_property PACKAGE_PIN J15 [get_ports {SEG_SELECT[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SEG_SELECT[3]}]

set_property PACKAGE_PIN N14 [get_ports {DEC_OUT[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {DEC_OUT[0]}]

set_property PACKAGE_PIN M14 [get_ports {DEC_OUT[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {DEC_OUT[1]}]

set_property PACKAGE_PIN L14 [get_ports {DEC_OUT[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {DEC_OUT[2]}]

set_property PACKAGE_PIN K14 [get_ports {DEC_OUT[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {DEC_OUT[3]}]

set_property PACKAGE_PIN J13 [get_ports {DEC_OUT[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {DEC_OUT[4]}]

set_property PACKAGE_PIN P14 [get_ports {DEC_OUT[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {DEC_OUT[5]}]

set_property PACKAGE_PIN R15 [get_ports {DEC_OUT[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {DEC_OUT[6]}]

### 6. 编译和下载

1. 将上述所有模块保存为相应的文件（如 `Generic_counter.v`, `Multiplexer.v`, `Seg7Decoder.v`, `Top_Module.v`）。
2. 使用Vivado或类似的FPGA开发工具打开项目，添加这些文件并设置顶层模块为 `Top_Module`。
3. 添加约束文件 `constraints.xdc` 并进行综合、实现和生成比特流文件。
4. 将生成的 `.bit` 文件加载到Basys 3 FPGA板上。

完成以上步骤后，你应该能够看到一个功能正常的十进制计时器，显示在7段显示器上。