用VHDL写出与门，或非门和编码器的代码

在VHDL语言中，逻辑门如与门、或非门以及编码器的设计通常使用结构体和过程来表示。这里我会给你提供一些基本的VHDL代码示例：

### 1. 与门 (AND Gate)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity AND_gate is
    Port ( A, B : in STD_LOGIC;
           Y   : out STD_LOGIC);
end AND_gate;

architecture Behavioral of AND_gate is
begin
    Y <= A and B;  -- 实现与逻辑
end Behavioral;

### 2. 或非门 (NOT Gate followed by OR Gate - NAND Gate)

entity NAND_gate is
    Port ( A, B : in STD_LOGIC;
           Y   : out STD_LOGIC);
end NAND_gate;

architecture Behavioral of NAND_gate is
begin
    Y <= not A or not B;  -- 实现非门后跟或门
end Behavioral;

### 3. 编码器 (4-2线编码器，例如DEMUX)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Encoder4to2 is
    Port (
        D : in std_logic_vector(3 downto 0);  -- 输入数据
        S : in std_logic_vector(1 downto 0);  -- 选择信号
        Q : out std_logic_vector(1 downto 0)); -- 输出二进制代码
end Encoder4to2;

architecture Behavioral of Encoder4to2 is
begin
    process(D, S)
    begin
        case S is
            when "00" => Q <= D(0) & D(1);
            when "01" => Q <= D(1) & D(2);
            when "10" => Q <= D(2) & D(3);
            when others => Q <= "00";  -- 默认输出00
        end case;
    end process;
end Behavioral;