xc7a100tfgg484 xdma pcie 管脚分配
时间: 2023-08-04 10:08:31 浏览: 272
XC7K325T PCIE XDMA 环境搭建及测试(含教程和FPGA工程上位机)
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以下是xc7a100tfgg484芯片与XDMA PCIe IP核之间的管脚分配示例:
1. PCIe时钟和复位
set_property -dict {PACKAGE_PIN U19 IOSTANDARD LVCMOS33} [get_ports {pcie_refclk_i}]
set_property -dict {PACKAGE_PIN U36 IOSTANDARD LVCMOS33} [get_ports {pcie_perstn_i}]
set_property -dict {PACKAGE_PIN U19 IOSTANDARD LVCMOS33} [get_ports {pcie_mgt_rstn_i}]
create_generated_clock -name pcie_ref_clk -source [get_ports {pcie_refclk_i}] -multiply_by 1 -divide_by 1 [get_ports {pcie_refclk_i}]
2. XDMA IP核与PCIE时钟和复位连接
connect_bd_net [get_bd_pins pcie4_0/WAKE_UP] [get_bd_pins system_i/proc_sys_reset_0/peripheral_reset_out]
connect_bd_net [get_bd_pins pcie4_0/pcie_gt_top_i/quad_gt_i/rxresetdoneout] [get_bd_pins system_i/proc_sys_reset_0/peripheral_reset_out]
connect_bd_net [get_bd_pins pcie4_0/pcie_gt_top_i/quad_gt_i/rxresetdoneout] [get_bd_pins system_i/proc_sys_reset_0/peripheral_reset_in]
connect_bd_net [get_bd_pins pcie4_0/pcie_gt_top_i/quad_gt_i/rxresetdoneout] [get_bd_pins system_i/proc_sys_reset_0/peripheral_aresetn]
3. XDMA IP核与PCIE数据通道连接
connect_bd_net [get_bd_pins pcie4_0/pcie_gt_top_i/quad_gt_i/rxd] [get_bd_pins axi_dma_0/s_axis_s2mm_tdata]
connect_bd_net [get_bd_pins pcie4_0/pcie_gt_top_i/quad_gt_i/rxc] [get_bd_pins axi_dma_0/s_axis_s2mm_tvalid]
connect_bd_net [get_bd_pins pcie4_0/pcie_gt_top_i/quad_gt_i/rxusrclk2] [get_bd_pins axi_dma_0/s_axis_s2mm_tready]
connect_bd_net [get_bd_pins axi_dma_0/m_axis_mm2s_tdata] [get_bd_pins pcie4_0/pcie_gt_top_i/quad_gt_i/txd]
connect_bd_net [get_bd_pins axi_dma_0/m_axis_mm2s_tvalid] [get_bd_pins pcie4_0/pcie_gt_top_i/quad_gt_i/txc]
connect_bd_net [get_bd_pins axi_dma_0/m_axis_mm2s_tready] [get_bd_pins pcie4_0/pcie_gt_top_i/quad_gt_i/txusrclk2]
4. XDMA IP核与PCIE地址通道连接
connect_bd_net [get_bd_pins pcie4_0/pcie_gt_top_i/quad_gt_i/rxaddr] [get_bd_pins axi_dma_0/s_axis_s2mm_tuser]
connect_bd_net [get_bd_pins pcie4_0/pcie_gt_top_i/quad_gt_i/rxvalid] [get_bd_pins axi_dma_0/s_axis_s2mm_tlast]
connect_bd_net [get_bd_pins axi_dma_0/m_axis_mm2s_tuser] [get_bd_pins pcie4_0/pcie_gt_top_i/quad_gt_i/txaddr]
connect_bd_net [get_bd_pins axi_dma_0/m_axis_mm2s_tlast] [get_bd_pins pcie4_0/pcie_gt_top_i/quad_gt_i/txvalid]
这些管脚分配可根据实际情况进行修改。
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