module test; typedef struct packed { logic [9:-1][2:0] a; //REQ-EXT-10001, REQ-EXT-10004 } ST1; typedef struct { ST1 st1; logic [2:0] b; } ST2; typedef struct { logic [31:0] c; } ST3; typedef struct { ST3 st3; ST2 st2_arr[3:0]; } ST4; initial begin ST2 st2; ST2 st2_1 = {3'b101, {ST1{10'b110}}, {ST1{20'b10101010101010}},{ST1{30'b1}}}; ST2 st2_2 = {3'b010, {ST1{10'b101}}, {ST1{20'b01010101010101}},{ST1{30'b0}}}; st2 = {2'b01, {3'b1, 3'b0, 12'b1}}; $display("%p",st2); //CHECK-001:'{a:'h1}, st2:'{'a:'h1}, '{a:'h0},'{a:h1}}} $display("st2_1:%p", st2_1); //CHECK-002 $display("st2_2:%p", st2_2); //CHECK-003 end endmodule when compiled by vcs, it says following verilog source has syntax error: "sc_assignment_pattern_035.sv",35: token is '{' ST2 st2_1 = '{3'b101, {ST1{10'B110}}, {ST1{20'b1010101010}},{ST1{30'b1}}}; //REQ-EXT-10201 1 error, how should I fix this syntax error? help me and thanks a lot!

The syntax error is caused by the curly braces ({}) around the ST1 struct initialization inside the ST2 struct initialization. To fix this, you should remove the curly braces and use just the ST1 struct initialization directly. Here's the corrected code:

module test;
    typedef struct packed {
        logic [9:-1][2:0] a; //REQ-EXT-10001, REQ-EXT-10004
    } ST1;
    
    typedef struct {
        ST1 st1;
        logic [2:0] b;
    } ST2;
    
    typedef struct {
        logic [31:0] c;
    } ST3;
    
    typedef struct {
        ST3 st3;
        ST2 st2_arr[3:0];
    } ST4;
    
    initial begin
        ST2 st2;
        ST2 st2_1 = {3'b101, ST1{10'b110}, ST1{20'b10101010101010}, ST1{30'b1}};
        ST2 st2_2 = {3'b010, ST1{10'b101}, ST1{20'b01010101010101}, ST1{30'b0}};
        st2 = {2'b01, {3'b1, 3'b0, 12'b1}};
        $display("%p",st2); //CHECK-001:'{a:'h1}, st2:'{'a:'h1}, '{a:'h0},'{a:h1}}}
        $display("st2_1:%p", st2_1); //CHECK-002
        $display("st2_2:%p", st2_2); //CHECK-003
    end
endmodule

Hope this helps!