Verilog代码实现AXI总线从DDR读取数据

module axi_ddr_read (
input wire clk, // 时钟信号
input wire rst, // 复位信号
input wire [31:0] address, // 读取数据的地址
output wire [31:0] data // 读取到的数据
);

// AXI总线接口
wire [31:0] axi_araddr; // 读取地址信号
wire axi_arvalid; // 读取有效信号
wire axi_arready; // 读取准备好信号
wire [31:0] axi_rdata; // 读取数据信号
wire axi_rvalid; // 读取数据有效信号
wire axi_rready; // 读取数据准备好信号

// AXI总线主机接口
axi_lite_master #(
.C_S_AXI_ADDR_WIDTH(32),
.C_S_AXI_DATA_WIDTH(32)
) inst_lite_master (
.ACLK(clk),
.ARESETn(rst),
.S_AXI_AWADDR(axi_araddr),
.S_AXI_AWVALID(axi_arvalid),
.S_AXI_AWREADY(axi_arready),
.S_AXI_WDATA(32'b0),
.S_AXI_WVALID(1'b0),
.S_AXI_WREADY(1'b0),
.S_AXI_BVALID(1'b0),
.S_AXI_BREADY(1'b0),
.S_AXI_ARADDR(address),
.S_AXI_ARVALID(axi_arvalid),
.S_AXI_ARREADY(axi_arready),
.S_AXI_RDATA(axi_rdata),
.S_AXI_RVALID(axi_rvalid),
.S_AXI_RREADY(axi_rready)
);

// 状态机
reg [1:0] state;
parameter IDLE = 2'b00, READ = 2'b01, WAIT = 2'b10;

always @(posedge clk) begin
if (rst) begin
state <= IDLE;
end else begin
case (state)
IDLE: begin
if (axi_arready) begin
state <= READ;
end else begin
state <= IDLE;
end
end
READ: begin
if (axi_rvalid) begin
state <= WAIT;
end else begin
state <= READ;
end
end
WAIT: begin
state <= IDLE;
end
endcase
end
end

// 数据输出
always @(posedge clk) begin
if (rst) begin
data <= 32'b0;
end else begin
case (state)
IDLE: begin
data <= 32'b0;
end
READ: begin
data <= axi_rdata;
end
WAIT: begin
data <= axi_rdata;
end
endcase
end
end

endmodule