锁存器和触发器vhdl代码

以下是锁存器和触发器的VHDL代码示例：

1. 锁存器代码示例：

library ieee;
use ieee.std_logic_1164.all;

entity latch1 is
    port (
        d   : in  std_logic;
        q   : out std_logic;
        ena : in  std_logic
    );
end latch1;

architecture example of latch1 is
    signal sig_save : std_logic := '0';
begin
    process(d, ena)
    begin
        if ena = '1' then
            sig_save <= d;
        end if;
        q <= sig_save;
    end process;
end example;

2. 触发器代码示例：

library ieee;
use ieee.std_logic_1164.all;

entity flip_flop is
    port (
        clk : in  std_logic;
        a   : in  std_logic;
        y   : out std_logic
    );
end flip_flop;

architecture example of flip_flop is
begin
    process(clk, a)
    begin
        if clk'event and clk = '1' then
            y <= a;
        end if;
    end process;
end example;