give me code what i need in lab 2

Certainly! Below is a summary of the key code snippets and steps you need to complete Lab 2 based on the provided document.

### Step-by-Step Code Summary for Lab 2

#### 1. **Setting Up the Project**
- Open Vivado and load the project from Part 1.
- Save it as a new project named "Part2" on your U: drive.
- Check and update the device settings if necessary (Project Settings -> Project Device).

#### 2. **Using All Digits on the Display**
- Download `drive_display.vhd` from Canvas.
- Replace the existing display entity with `drive_display`.

**Entity Declaration for `drive_display`:**

entity drive_display is
    Port (
        CLK100MHZ : in std_logic;
        display : in STD_LOGIC_VECTOR(31 downto 0);
        DIGITS : out STD_LOGIC_VECTOR(7 downto 0);
        SEGMENTS : out STD_LOGIC_VECTOR(7 downto 0)
    );
end drive_display;

**Top-Level VHDL File Changes:**

-- Declare the display signal
signal display : std_logic_vector(31 downto 0) := x"01234567";

-- Instantiate the drive_display component
drive_display_inst : entity work.drive_display
    port map (
        CLK100MHZ => CLK100MHZ,
        display => display,
        DIGITS => DIGITS,
        SEGMENTS => SEGMENTS
    );

-- Synthesize and verify the display

#### 3. **Adding the Display to ALU Inputs and Outputs**
- Modify the display signal to show specific parts of the ALU operation.

**Example Assignment in Architecture:**

-- Assign display signal to show ALU inputs and outputs
display <= "0000" & opcode & "0000" & result & "0000" & input2 & "0000" & input1;

-- Example:
-- digit 6: shows the opcode
-- digit 4: shows the result
-- digit 2: shows the second input
-- digit 0: shows the first input

#### 4. **Making Better Use of the Simulator: Testbenches**
- Download `testbench.vhd` from Canvas and add it as a simulation source.
- Copy the project to the C: drive due to software conflicts with the U: drive.

**Testbench Example (`testbench.vhd`):**

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity tb is
end tb;

architecture Behavioral of tb is
    signal CLK100MHZ : std_logic := '0';
    signal BTNL, BTNR, BTNU, BTND, BTNC : std_logic;
    signal SWITCHES : STD_LOGIC_VECTOR(15 downto 0);
    signal LEDS : STD_LOGIC_VECTOR(15 downto 0);
    signal DIGITS : STD_LOGIC_VECTOR(7 downto 0);
    signal SEGMENTS : STD_LOGIC_VECTOR(7 downto 0);

begin
    -- Instantiate the unit under test (UUT)
    uut : entity work.micro(Behavioral)
        port map (
            CLK100MHZ => CLK100MHZ,
            BTNL => BTNL,
            BTNR => BTNR,
            BTNU => BTNU,
            BTND => BTND,
            BTNC => BTNC,
            SWITCHES => SWITCHES,
            LEDS => LEDS,
            DIGITS => DIGITS,
            SEGMENTS => SEGMENTS
        );

    -- Clock process
    CLK100MHZ <= not CLK100MHZ after 5 ns;

    -- Stimulus process
    stim_proc : process
    begin
        -- Initial conditions
        SWITCHES <= "0000000000000000";
        BTNL <= '1';
        wait for 100 ns;

        -- Change inputs
        SWITCHES <= "0001000000010001";
        wait;
    end process;
end Behavioral;

#### 5. **Personalizing the ALU to Your Student ID**
- Determine the opcodes based on the last digit of your student ID.
- Implement the logic to handle these opcodes in your ALU.

**Opcode Table (Example for ID ending in 2):**

| Operation       | Opcode |
|-----------------|--------|
| num1 + num2     | 0001   |
| num1 - num2     | 1111   |
| num2 - num1     | 0011   |
| num1            | 0101   |
| num1 AND num2   | 1100   |
| num1 OR num2    | 0010   |
| num1 XOR num2   | 0111   |
| abs(num1)       | 1110   |

**ALU Logic Example:**

process(opcode, input1, input2)
begin
    case opcode is
        when "0001" => result <= input1 + input2;
        when "1111" => result <= input1 - input2;
        when "0011" => result <= input2 - input1;
        when "0101" => result <= input1;
        when "1100" => result <= input1 and input2;
        when "0010" => result <= input1 or input2;
        when "0111" => result <= input1 xor input2;
        when "1110" => result <= abs(input1);
        when others => result <= (others => '0'); -- Unrecognized opcode
    end case;
end process;

#### 6. **Uploading Your Final Result**
- Run simulations to verify the correct operation of your ALU with personalized data.
- Upload your final code and simulation results to the Canvas assignment for Lab 2.
- Ensure your project is saved on your U: drive for future access.

By following these steps and using the provided code snippets, you should be able to complete Lab 2 successfully.