module sreg_sipo #(parameter N = 8)( input sys_clk, input sys_rst_n, input sin, input rd, output [N - 1 : 0] sout ); // 请在下面添加代码，完成8位串入并出移位寄存器（左移）的建模 // 代码量预计6行 /****** Begin / / End ******/ endmodule预期输出： VCD info: dumpfile waveform.vcd opened for output. At time 0ns: sys_rst_n = 0, sin = 0, rd = 0, sout = 00000000 At time 20ns: sys_rst_n = 1, sin = 0, rd = 0, sout = 00000000 At time 35ns: sys_rst_n = 1, sin = 1, rd = 0, sout = 00000000 At time 95ns: sys_rst_n = 1, sin = 0, rd = 1, sout = 00111111

module sreg_sipo #(parameter N = 8)(
input sys_clk,
input sys_rst_n,
input sin,
input rd,
output [N - 1 : 0] sout
);

reg [N - 1 : 0] shift_reg;

always @(posedge sys_clk) begin
if (!sys_rst_n) begin
shift_reg <= 0;
end else begin
shift_reg <= {shift_reg[N-2:0], sin};
end
end

assign sout = rd ? shift_reg : {N{1'b0}}; //当rd为1时，输出移位寄存器的值，否则输出0

endmodule

//测试模块
module testbench();
reg sys_clk, sys_rst_n, sin, rd;
wire [7:0] sout;

sreg_sipo #(.N(8)) uut(
.sys_clk(sys_clk),
.sys_rst_n(sys_rst_n),
.sin(sin),
.rd(rd),
.sout(sout)
);

initial begin
$dumpfile("waveform.vcd");
$dumpvars(0, testbench);
sys_rst_n <= 0;
sys_clk <= 0;
sin <= 0;
rd <= 0;
#20 sys_rst_n <= 1;
#15 sin <= 1;
#60 rd <= 1;
#10 $finish;
end

always #10 sys_clk <= ~sys_clk;

endmodule