用quartus生成十进制计数器的代码

以下是使用Quartus生成十进制计数器的VHDL代码：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity decimal_counter is
    Port (
        clk : in STD_LOGIC;
        reset : in STD_LOGIC;
        count : out STD_LOGIC_VECTOR (3 downto 0)
    );
end entity;

architecture Behavioral of decimal_counter is
    signal temp_count : unsigned(3 downto 0) := (others => '0');
begin
    process (clk, reset)
    begin
        if reset = '1' then
            temp_count <= (others => '0');
        elsif rising_edge(clk) then
            if temp_count = 9 then
                temp_count <= (others => '0');
            else
                temp_count <= temp_count + 1;
            end if;
        end if;
    end process;

    count <= std_logic_vector(temp_count);
end architecture;

该代码使用一个名为`temp_count`的无符号变量来存储计数器的值。在每个上升沿时，如果`temp_count`的值为9，则将其重置为0。否则，`temp_count`将增加1。最后，`temp_count`被转换为`std_logic_vector`类型并输出到`count`端口。