Consider two 4-bit binary numbers A and B. Bits of A are a3, a2, a1, and a0, and bits of B are b3, b2, b1, and b0. A is greater than B if a3 is 1 and b3 is 0, but if a3 and b3 are the same, then if a2 is 1 and b2 is 0, we can determine that A is greater than B. This evaluation continues until a0 and b0 are considered. If a0 and b0 are equal then A and B are equal. Using discrete gates and Verilog gate primitives build a 4-bit comparator that generates a 1 on its GT output when its 4-bit input A is greater than its B input, and a 1 on its EQ output when A and B are equal. Use the generate statement and other Verilog iterative logic support structures.

Here is the Verilog code for a 4-bit comparator that generates a 1 on its GT output when A is greater than B and a 1 on its EQ output when A and B are equal:

module comparator(A, B, GT, EQ);
  input [3:0] A, B;
  output GT, EQ;

  assign GT = (A[3] & ~B[3]) | (A[3] == B[3] && A[2] & ~B[2]) | 
              (A[3:2] == B[3:2] && A[1] & ~B[1]) | (A == B);
  assign EQ = (A == B);

endmodule

In this code, the `assign` statement for `GT` uses a series of logical operations to compare the bits of A and B starting with the most significant bit. If the most significant bit of A is 1 and the most significant bit of B is 0, then A is greater than B. If the most significant bits of A and B are the same, then the comparison continues with the second most significant bit, and so on until all four bits have been compared. If the bits of A and B are equal, then `EQ` is set to 1.