verilog实现FIFO代码

以下是一个简单的 Verilog 实现 FIFO 的代码：

module fifo (
input clk,
input rst,
input wr_en,
input rd_en,
input [7:] data_in,
output [7:] data_out,
output empty,
output full
);

parameter WIDTH = 8;
parameter DEPTH = 16;

reg [WIDTH-1:] mem [:DEPTH-1];
reg [4:] wr_ptr = ;
reg [4:] rd_ptr = ;
reg [4:] count = ;

assign empty = (count == );
assign full = (count == DEPTH);

always @(posedge clk) begin
if (rst) begin
wr_ptr <= ;
rd_ptr <= ;
count <= ;
end else begin
if (wr_en && !full) begin
mem[wr_ptr] <= data_in;
wr_ptr <= wr_ptr + 1;
count <= count + 1;
end
if (rd_en && !empty) begin
data_out <= mem[rd_ptr];
rd_ptr <= rd_ptr + 1;
count <= count - 1;
end
end
end

endmodule

希望能对你有所帮助！