用verilog给我一个uart接口代码

下面是一个简单的UART接口的Verilog代码：

module uart_interface
(
input clk, //输入时钟
input reset, //复位信号
input tx_data_ready, //传输数据准备好信号
output tx_data, //传输数据信号
input rx_data, //接收数据信号
output rx_data_ready //接收数据准备好信号
);

parameter BAUD_RATE = 9600; //波特率
parameter CLOCK_FREQUENCY = 100000000; //时钟频率

reg [7:0] tx_byte; //发送字节
reg tx_busy; //发送忙标志
reg [7:0] rx_byte; //接收字节
reg rx_busy; //接收忙标志
reg [3:0] tx_state; //发送状态
reg [3:0] rx_state; //接收状态
reg [31:0] tx_count; //发送计数器
reg [31:0] rx_count; //接收计数器

assign tx_data = tx_byte[0]; //将发送字节的最低位赋给传输数据信号

always @(posedge clk or posedge reset)
begin
if (reset)
begin
tx_byte <= 8'b0;
tx_busy <= 1'b0;
rx_byte <= 8'b0;
rx_busy <= 1'b0;
tx_state <= 4'b0000;
rx_state <= 4'b0000;
tx_count <= 32'd0;
rx_count <= 32'd0;
end
else
begin
//发送状态机
case (tx_state)
4'b0000: //等待数据准备好
if (tx_data_ready)
begin
tx_byte <= 8'b0;
tx_busy <= 1'b1;
tx_state <= 4'b0001;
end
4'b0001: //发送起始位
begin
tx_byte <= 8'b0;
tx_busy <= 1'b1;
tx_state <= 4'b0010;
end
4'b0010: //发送数据位
begin
tx_byte <= {tx_count, tx_data, 1'b1};
tx_count <= tx_count + 1;
if (tx_count >= BAUD_RATE)
begin
tx_count <= 0;
tx_state <= 4'b0011;
end
end
4'b0011: //发送停止位
begin
tx_byte <= 8'b1;
tx_busy <= 1'b0;
tx_state <= 4'b0000;
end
endcase

//接收状态机
case (rx_state)
4'b0000: //等待起始位
if (!rx_data)
begin
rx_byte <= 8'b0;
rx_busy <= 1'b1;
rx_count <= 0;
rx_state <= 4'b0001;
end
4'b0001: //接收数据位
begin
if (rx_count < BAUD_RATE)
begin
rx_byte <= {rx_byte[6:0], rx_data};
rx_count <= rx_count + 1;
end
else
begin
rx_busy <= 1'b0;
rx_state <= 4'b0000;
end
end
endcase
end
end

assign rx_data_ready = rx_busy; //接收忙标志赋给接收数据准备好信号

endmodule