EP4CE6F17C8数码显示verilog

以下是EP4CE6F17C8数码显示的Verilog代码示例：

module seven_segment_display(
    input wire clk,
    input wire rst,
    output reg [6:0] seg,
    output reg dp
);

reg [3:0] count = 4'b0000;
reg [6:0] display_data = 7'b0000000;

always @(posedge clk) begin
    if (rst) begin
        count <= 4'b0000;
        display_data <= 7'b0000000;
    end
    else begin
        if (count == 4'b1001) begin
            count <= 4'b0000;
            display_data <= display_data + 1;
        end
        else begin
            count <= count + 1;
        end
    end
end

always @(display_data) begin
    case (display_data)
        7'b0000000: seg <= 7'b1000000; // 0
        7'b0000001: seg <= 7'b1111001; // 1
        7'b0000010: seg <= 7'b0100100; // 2
        7'b0000011: seg <= 7'b0110000; // 3
        7'b0000100: seg <= 7'b0011001; // 4
        7'b0000101: seg <= 7'b0010010; // 5
        7'b0000110: seg <= 7'b0000010; // 6
        7'b0000111: seg <= 7'b1111000; // 7
        7'b0001000: seg <= 7'b0000000; // 8
        7'b0001001: seg <= 7'b0010000; // 9
        7'b0001010: seg <= 7'b0001000; // A
        7'b0001011: seg <= 7'b0000011; // b
        7'b0001100: seg <= 7'b1000110; // C
        7'b0001101: seg <= 7'b0100001; // d
        7'b0001110: seg <= 7'b0000110; // E
        7'b0001111: seg <= 7'b0001110; // F
        default: seg <= 7'b1111111; // Off
    endcase
end

endmodule