预期输出: VCD info: dumpfile waveform.vcd opened for output. At time 0ns: sys_rst_n = 0, sin = 0, rd = 0, sout = 00000000 At time 20ns: sys_rst_n = 1, sin = 0, rd = 0, sout = 00000000 At time 35ns: sys_rst_n = 1, sin = 1, rd = 0, sout = 00000000 At time 95ns: sys_rst_n = 1, sin = 0, rd = 1, sout = 00111111
时间: 2023-12-13 08:03:37 浏览: 19
这是一个仿真结果的输出,其中包括了时刻(time)、信号名称(sys_rst_n、sin、rd、sout)以及对应的值。这个输出表明在仿真过程中,系统复位信号先被置为低电平,然后在时刻20ns被置为高电平。在时刻35ns时,输入信号sin被置为高电平,而rd信号仍为低电平。最后,在时刻95ns时,rd信号被置为高电平,同时输出信号sout的值为00111111。这个输出结果可以用于检查仿真是否正确以及对设计进行调试。
相关问题
module sreg_sipo #(parameter N = 8)( input sys_clk, input sys_rst_n, input sin, input rd, output [N - 1 : 0] sout ); // 请在下面添加代码,完成8位串入并出移位寄存器(左移)的建模 // 代码量预计6行 /****** Begin / / End ******/ endmodule预期输出: VCD info: dumpfile waveform.vcd opened for output. At time 0ns: sys_rst_n = 0, sin = 0, rd = 0, sout = 00000000 At time 20ns: sys_rst_n = 1, sin = 0, rd = 0, sout = 00000000 At time 35ns: sys_rst_n = 1, sin = 1, rd = 0, sout = 00000000 At time 95ns: sys_rst_n = 1, sin = 0, rd = 1, sout = 00111111
module sreg_sipo #(parameter N = 8)(
input sys_clk,
input sys_rst_n,
input sin,
input rd,
output [N - 1 : 0] sout
);
reg [N - 1 : 0] shift_reg;
always @(posedge sys_clk) begin
if (!sys_rst_n) begin
shift_reg <= 0;
end else begin
shift_reg <= {shift_reg[N-2:0], sin};
end
end
assign sout = rd ? shift_reg : {N{1'b0}}; //当rd为1时,输出移位寄存器的值,否则输出0
endmodule
//测试模块
module testbench();
reg sys_clk, sys_rst_n, sin, rd;
wire [7:0] sout;
sreg_sipo #(.N(8)) uut(
.sys_clk(sys_clk),
.sys_rst_n(sys_rst_n),
.sin(sin),
.rd(rd),
.sout(sout)
);
initial begin
$dumpfile("waveform.vcd");
$dumpvars(0, testbench);
sys_rst_n <= 0;
sys_clk <= 0;
sin <= 0;
rd <= 0;
#20 sys_rst_n <= 1;
#15 sin <= 1;
#60 rd <= 1;
#10 $finish;
end
always #10 sys_clk <= ~sys_clk;
endmodule
// SYS_CLK_FREQ表示输入时钟频率;TARGET_CLK_FREQ表示目标时钟频率;N表示计数器的位宽 module clkdiv #(parameter SYS_CLK_FREQ = 100_000_000, TARGET_CLK_FREQ = 10_000_000, N = 3)( input sys_clk, input sys_rst_n, output clk_out ); // 请在下面添加代码,对输入时钟(100MHz)进行10分频 // 代码量预计10~13行 /****** Begin / / End ******/ endmodule输入信号: 时钟周期为10ns(100MHz); 0ns: sys_clk = 0, sys_rst_n = 0; 20ns: sys_rst_n = 1; 复位信号无效后,再经历20个时钟上升沿。 预期输出: VCD info: dumpfile waveform.vcd opened for output. At time 0ns: sys_rst_n = 0, clk_out = x At time 5ns: sys_rst_n = 0, clk_out = 0 At time 20ns: sys_rst_n = 1, clk_out = 0 At time 65ns: sys_rst_n = 1, clk_out = 1 At time 115ns: sys_rst_n = 1, clk_out = 0 At time 165ns: sys_rst_n = 1, clk_out = 1 At time 215ns: sys_rst_n = 1, clk_out = 0
module clkdiv #(parameter SYS_CLK_FREQ = 100_000_000, TARGET_CLK_FREQ = 10_000_000, N = 3)(
input sys_clk,
input sys_rst_n,
output clk_out
);
reg [N-1:0] counter;
reg clk_div;
// 初始化计数器和分频信号
initial begin
counter = 0;
clk_div = 0;
end
always @(posedge sys_clk or negedge sys_rst_n) begin
if (!sys_rst_n) begin
counter <= 0;
clk_div <= 0;
end
else begin
counter <= counter + 1;
if (counter >= SYS_CLK_FREQ / TARGET_CLK_FREQ - 1) begin
counter <= 0;
clk_div <= ~clk_div;
end
end
end
assign clk_out = clk_div;
endmodule
// 代码解释:
// 通过一个计数器对输入时钟进行计数,当计数器达到一定值时,翻转分频信号
// 分频信号的翻转频率为目标时钟频率,即输入时钟的1/N