编写verilog代码,实现交通灯左转绿灯
时间: 2024-06-06 20:10:59 浏览: 8
module traffic_light(input clk, //时钟信号
input reset, //复位信号
output reg red, //红灯信号
output reg yellow, //黄灯信号
output reg green_left); //左转绿灯信号
//定义状态
parameter RED = 2'b00;
parameter YELLOW = 2'b01;
parameter GREEN_LEFT = 2'b10;
parameter GREEN_STRAIGHT = 2'b11;
//定义状态寄存器和下一个状态寄存器
reg [1:0] state, next_state;
//状态转移条件
always @(*) begin
case(state)
RED: begin
next_state = GREEN_LEFT;
end
YELLOW: begin
next_state = RED;
end
GREEN_LEFT: begin
next_state = YELLOW;
end
GREEN_STRAIGHT: begin
next_state = RED;
end
default: begin
next_state = RED;
end
endcase
end
//状态寄存器更新
always @(posedge clk, posedge reset) begin
if(reset) begin
state <= RED;
end
else begin
state <= next_state;
end
end
//输出逻辑
always @(*) begin
case(state)
RED: begin
red = 1;
yellow = 0;
green_left = 0;
end
YELLOW: begin
red = 0;
yellow = 1;
green_left = 0;
end
GREEN_LEFT: begin
red = 0;
yellow = 0;
green_left = 1;
end
GREEN_STRAIGHT: begin
red = 1;
yellow = 1;
green_left = 0;
end
default: begin
red = 1;
yellow = 0;
green_left = 0;
end
endcase
end
endmodule