I2C总线模块，fpga代码

以下是一个简单的I2C总线模块的FPGA代码示例，供参考：

module i2c_master(
    input clk,
    input rst,
    input sda, // I2C 数据线
    input scl, // I2C 时钟线
    output reg [7:0] data_out,
    output reg ack_out,
    input [7:0] data_in,
    input ack_in
);

reg [7:0] data_reg;
reg sda_out;
reg scl_out;
reg [3:0] state;

assign sda = sda_out;
assign scl = scl_out;

parameter IDLE = 4'd0;
parameter START = 4'd1;
parameter WRITE_ADDR = 4'd2;
parameter WRITE_DATA = 4'd3;
parameter READ_DATA = 4'd4;
parameter STOP = 4'd5;

always @(posedge clk) begin
    if (rst) begin
        data_reg <= 8'b0;
        ack_out <= 1'b0;
        sda_out <= 1'b1;
        scl_out <= 1'b1;
        state <= IDLE;
    end else begin
        case (state)
            IDLE: begin
                if (data_in != 8'b0) begin
                    data_reg <= data_in;
                    state <= START;
                end
            end
            START: begin
                sda_out <= 1'b0;
                scl_out <= 1'b0;
                state <= WRITE_ADDR;
            end
            WRITE_ADDR: begin
                sda_out <= 1'b0;
                scl_out <= 1'b1;
                state <= WRITE_DATA;
            end
            WRITE_DATA: begin
                sda_out <= data_reg[7];
                scl_out <= 1'b0;
                data_reg <= {data_reg[6:0], 1'b0};
                state <= ACK;
            end
            READ_DATA: begin
                sda_out <= 1'b1;
                scl_out <= 1'b0;
                data_out <= data_reg;
                state <= STOP;
            end
            STOP: begin
                sda_out <= 1'b0;
                scl_out <= 1'b1;
                state <= IDLE;
            end
            default: state <= IDLE;
        endcase
    end
end

always @(posedge clk) begin
    if (rst) begin
        ack_out <= 1'b0;
    end else begin
        case (state)
            WRITE_ADDR, WRITE_DATA: begin
                if (scl == 1'b1 && sda == 1'b0) begin
                    ack_out <= 1'b1;
                end else begin
                    ack_out <= 1'b0;
                end
            end
            READ_DATA: begin
                if (scl == 1'b1 && ack_in == 1'b1) begin
                    state <= STOP;
                end
            end
            STOP: begin
                ack_out <= 1'b0;
            end
            default: ack_out <= 1'b0;
        endcase
    end
end

endmodule

该模块支持读写操作，可以通过输入不同的数据来实现不同的操作。需要注意的是，这只是一个简单的示例代码，实际应用中需要根据具体的需求进行修改和优化。