fir低通滤波fpga代码

以下是FPGA实现的FIR低通滤波器代码：

module fir_lowpass_filter(
    input clk,
    input rst,
    input signed [15:0] data_in,
    output reg signed [15:0] data_out
);

parameter TAP_LENGTH = 16;
parameter COEFFICIENTS[TAP_LENGTH] = '{8'h00, 8'h01, 8'h02, 8'h03, 8'h04, 8'h05, 8'h06, 8'h07, 8'h08, 8'h09, 8'h0A, 8'h0B, 8'h0C, 8'h0D, 8'h0E, 8'h0F};

reg signed [15:0] delay_line[TAP_LENGTH];
reg signed [15:0] sum;

integer i;

always @(posedge clk) begin
    if (rst == 1) begin
        for (i = 0; i < TAP_LENGTH; i = i + 1) begin
            delay_line[i] <= 0;
        end
        sum <= 0;
        data_out <= 0;
    end else begin
        for (i = TAP_LENGTH-1; i > 0; i = i - 1) begin
            delay_line[i] <= delay_line[i-1];
        end
        delay_line[0] <= data_in;
        sum <= 0;
        for (i = 0; i < TAP_LENGTH; i = i + 1) begin
            sum <= sum + delay_line[i] * COEFFICIENTS[i];
        end
        data_out <= sum;
    end
end

endmodule

该代码实现了一个16阶的FIR低通滤波器，使用8位系数。数据输入和输出都是16位带符号整数。在每个时钟上升沿时，输入数据将被送入延迟线，然后乘以系数并加总。输出是加总的结果。在重置信号为高时，延迟线和累加器将被清零。系数在代码中定义为参数。