cortex_M3处理器初始化使能代码

以下是 Cortex-M3 处理器初始化使能代码的示例：

#include "stm32f10x.h"

void SystemInit(void)
{
  /* Reset the RCC clock configuration to the default reset state */
  /* Set HSION bit */
  RCC->CR |= (uint32_t)0x00000001;

  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
  RCC->CFGR &= (uint32_t)0xF8FF0000;

  /* Reset HSEON, CSSON and PLLON bits */
  RCC->CR &= (uint32_t)0xFEF6FFFF;

  /* Reset HSEBYP bit */
  RCC->CR &= (uint32_t)0xFFFBFFFF;

  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
  RCC->CFGR &= (uint32_t)0xFF80FFFF;

  /* Disable all interrupts and clear pending flags */
  RCC->CIR = 0x009F0000;

  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
  /* PLL configuration */
  /* PLLCLK = HSE * PLLMUL */
  /* SYSCLK = PLLCLK / HCLK_DIV */
  RCC->CFGR |= (uint32_t)0x001D0400;
  RCC->CFGR2 &= (uint32_t)0xFFFFFFF8;
  RCC->CFGR2 |= (uint32_t)0x00000002;

  /* Enable HSE */
  RCC->CR |= RCC_CR_HSEON;

  /* Wait till HSE is ready */
  while ((RCC->CR & RCC_CR_HSERDY) == 0);

  /* Enable PLL */
  RCC->CR |= RCC_CR_PLLON;

  /* Wait till PLL is ready */
  while ((RCC->CR & RCC_CR_PLLRDY) == 0);

  /* Select PLL as system clock source */
  RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
  RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;

  /* Wait till PLL is used as system clock source */
  while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08);
}

这段代码是针对STM32F10x系列微控制器的，其中包含了时钟配置、PLL配置、中断配置等初始化操作。可以根据需要进行修改和适配。