module ztj_609 ( input clk, reset, input data_in, output reg data_out ); parameter S0 = 2'b00; // Start parameter S1 = 2'b01; // 1 parameter S2 = 2'b10; // 11 parameter S3 = 2'b11; // 110 parameter S4 = 2'b100; // 1101 reg [1:0] state; always @(posedge clk or negedge reset) begin if (reset == 0) begin state <= S0; data_out <= 0; end else begin case(state) S0: if (data_in == 1) state <= S0; else state <= S1; S1: if (data_in == 1) state <= S2; else state <= S1; S2: if (data_in == 1) state <= S3; else state <= S1; S3: if (data_in == 1) state <= S4; else state <= S1; S4: if (data_in == 1) begin state <= S0; data_out <= 1; end else state <= S1; endcase end end endmodule 写出这段代码的测试文件

以下是这段代码的测试文件，包括了时钟信号的生成和对数据输入输出的测试：

module ztj_609_tb;
    reg clk, reset, data_in;
    wire data_out;

    ztj_609 uut (
        .clk(clk),
        .reset(reset),
        .data_in(data_in),
        .data_out(data_out)
    );

    initial begin
        clk = 0;
        forever #10 clk = ~clk;
    end

    initial begin
        reset = 1;
        data_in = 0;
        #20 reset = 0;
    end

    initial begin
        // Test case 1
        data_in = 0;
        #10 data_in = 1;
        #10 data_in = 0;
        #10 data_in = 1;
        #10 data_in = 1;
        #10 data_in = 0;
        #10 data_in = 1;
        #10 data_in = 0;
        #10 data_in = 1;
        #10 $display("Test case 1: Expected output = 1, Actual output = %b", data_out);

        // Test case 2
        data_in = 0;
        #10 data_in = 1;
        #10 data_in = 1;
        #10 data_in = 0;
        #10 data_in = 1;
        #10 data_in = 1;
        #10 data_in = 0;
        #10 data_in = 1;
        #10 data_in = 0;
        #10 data_in = 1;
        #10 $display("Test case 2: Expected output = 0, Actual output = %b", data_out);

        // Test case 3
        data_in = 0;
        #10 data_in = 1;
        #10 data_in = 0;
        #10 data_in = 0;
        #10 data_in = 1;
        #10 data_in = 1;
        #10 data_in = 0;
        #10 data_in = 1;
        #10 data_in = 0;
        #10 data_in = 1;
        #10 $display("Test case 3: Expected output = 1, Actual output = %b", data_out);

        $finish;
    end
endmodule