用Verilog写一个偶数分频

module even_divider(
input clk_in,
output reg clk_out
);

reg [31:0] count;

always @(posedge clk_in) begin
if(count == 1) begin
clk_out <= ~clk_out;
count <= 0;
end else begin
count <= count + 1;
end
end

endmodule

// 2分频测试代码
module test_even_divider;
reg clk_in;
wire clk_out;

even_divider uut(
.clk_in(clk_in),
.clk_out(clk_out)
);

initial begin
$dumpfile("test_even_divider.vcd");
$dumpvars(0, test_even_divider);
clk_in <= 0;
#5;
repeat(10) begin
clk_in <= ~clk_in;
#10;
end
$finish;
end
endmodule